{"id":814665,"url":"http://patchwork.ozlabs.org/api/covers/814665/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/cover/20170917164523.6970-1-martin.blumenstingl@googlemail.com/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","list_archive_url":null,"date":"2017-09-17T16:45:17","name":"[v7,0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/?format=json","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-imx/cover/20170917164523.6970-1-martin.blumenstingl@googlemail.com/mbox/","series":[{"id":3526,"url":"http://patchwork.ozlabs.org/api/series/3526/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=3526","date":"2017-09-17T16:45:17","name":"SMP and CPU hotplug support for Meson8/Meson8b","version":7,"mbox":"http://patchwork.ozlabs.org/series/3526/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/814665/comments/","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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\n\tSun, 17 Sep 2017 09:45:49 -0700 (PDT)","From":"Martin Blumenstingl ","To":"linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, \n\tkhilman@baylibre.com, carlo@caione.org, linux@armlinux.org.uk","Subject":"[PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","Date":"Sun, 17 Sep 2017 18:45:17 +0200","Message-Id":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","X-Mailer":"git-send-email 2.14.1","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170917_094614_799968_BA59C70E ","X-CRM114-Status":"GOOD ( 21.87 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (martin.blumenstingl[at]googlemail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tarnd@arndb.de, Martin Blumenstingl , \n\trobh+dt@kernel.org","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"This patchset adds support for booting the secondary CPU cores (and\ntaking them offline again) on Amlogic Meson8 and Meson8b SoCs.\nIt is based on an earlier version from Carlo Caione - this helped me\na lot to get a better understanding of how SMP/CPU hotplug works\n(compared to the code found in Amlogic's GPL kernel sources from\nyear 2015).\n\nChanges since v6 from [6]:\n- rebased on top of v4.14-rc1 (which only corrected some line\n numbers in the SCU patches)\n\nChanges since v5 from [5]:\n- dropped dependency on another patch series (for the clock\n controller's embedded reset controller, which is needed to boot\n the secondary CPUs) from the cover-letter as that series is now\n merged\n- fix incorrect documentation of scu_cpu_power_enable (thanks to\n Russell King for spotting these). removed the paragraph about\n preemption, cache coherency and interrupts as we're powering on\n a CPU core (the text was copied from the original scu_power_mode\n but simply not adjusted). also changed \"Set the executing CPUs\"\n to \"Set the given (logical) CPU's\" as we're not modifying the\n current CPU. this affects only patch #2\n- extended the commit message of patch #3 with a short sentence\n about why SCU_CPU_STATUS_MASK was introduced\n\nChanges since v4 from [4]:\n- use __pa_symbol(secondary_startup) instead of\n virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n (affects patch #4)\n- (cover-letter) removed dependency on my other patch\n \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n was merged into Kevin's Amlogic repo today\n- dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n lines\") again because the reset controller series exposes the\n preprocessor macros now directly, see [1]\n- refreshed the .dts patches so they now include the new header for\n the reset line preprocessor macros\n\nChanges since v3 from [3]:\n- added Rob's ACK to patch #1\n- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n- removed all \"pen\" code from patch #4 as that code was not needed\n at all (it was left-over while trying to fix Meson8 secondary CPU\n boot - which turned out to have nothing to do with this \"pen\" code)\n- removed all memory barrier operations as they were added based on\n the code in the Amlogic GPL kernel tree (while trying to fix the\n Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n still works fine with these on my Meson8m2 and Meson8b boards.\n- added PATCH #5 as we now have to export the reset identifiers\n (just like we do it with the clock identifiers / preprocessor\n macros) - this is the result of a change in the reset controller\n patch in version 2, see [1]\n- use the reset line preprocessor macros (from patch #5) in patches\n #6 and #7\n\nChanges since v2 from [0]:\n- added support for Meson8 (which requires a slightly different\n enable-method)\n- implemented CPU hotplug support which allows taking a CPU core\n offline for both, Meson8 and Meson8b\n- add a function to smp_scu.c which allows enabling a CPU core from\n a different CPU (previously only the power mode for the current CPU\n could be changed). Without this the CPU cores on Meson8 won't come\n up (Amlogic's vendor GPL kernel sources also enable power through\n SCU as very first step for Meson8b as well)\n- add a function to smp_scu.c to get the power status of a CPU core\n (which is needed because the code in .cpu_kill needs to wait until\n the core is actually powered off)\n- dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n as it is already applied (for both, Meson8 and Meson8b)\n- dropped the patches which implement the reset controller which is\n built into the clock-controller, these are a separate series: [1]\n- moved the enable-method property to each CPU node\n\n\n[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n[4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n[5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n\nCarlo Caione (2):\n dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n ARM: dts: meson8b: add support for booting the secondary CPU cores\n\nMartin Blumenstingl (4):\n ARM: smp_scu: add a helper for powering on a specific CPU\n ARM: smp_scu: allow the platform code to read the SCU CPU status\n ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n ARM: dts: meson8: add support for booting the secondary CPU cores\n\n .../devicetree/bindings/arm/amlogic/pmu.txt | 18 +\n .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 ++\n Documentation/devicetree/bindings/arm/cpus.txt | 2 +\n arch/arm/Makefile | 1 +\n arch/arm/boot/dts/meson8.dtsi | 21 +\n arch/arm/boot/dts/meson8b.dtsi | 21 +\n arch/arm/include/asm/smp_scu.h | 12 +\n arch/arm/kernel/smp_scu.c | 43 +-\n arch/arm/mach-meson/Kconfig | 1 +\n arch/arm/mach-meson/Makefile | 1 +\n arch/arm/mach-meson/platsmp.c | 440 +++++++++++++++++++++\n 11 files changed, 586 insertions(+), 6 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt\n create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt\n create mode 100644 arch/arm/mach-meson/platsmp.c"}