{"id":814452,"url":"http://patchwork.ozlabs.org/api/covers/814452/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20170916023417.14599-1-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170916023417.14599-1-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-16T02:34:11","name":"[v3,0/6] TCG vectorization and example conversion","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20170916023417.14599-1-richard.henderson@linaro.org/mbox/","series":[{"id":3407,"url":"http://patchwork.ozlabs.org/api/series/3407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3407","date":"2017-09-16T02:34:11","name":"TCG vectorization and example conversion","version":3,"mbox":"http://patchwork.ozlabs.org/series/3407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/814452/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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I now expose TCGv_vec\nto target front-ends, but opaque wrt the vector size. One can thus\ncompose vector operations, as demonstrated in target/arm/.\n\nThe actual host vector length now becomes an argument to the *_vec\nopcodes. It's a little awkward, but does prevent an explosion of\nopcode values.\n\nAll R-b dropped because all patches rewritten or heavily modified.\n\nWhacha think?\n\n\nr~\n\n\nRichard Henderson (6):\n tcg: Add types and operations for host vectors\n tcg: Add vector expanders\n target/arm: Align vector registers\n target/arm: Use vector infrastructure for aa64 add/sub/logic\n tcg/i386: Add vector operations\n tcg/aarch64: Add vector operations\n\n Makefile.target | 2 +-\n accel/tcg/tcg-runtime.h | 24 ++\n target/arm/cpu.h | 2 +-\n tcg/aarch64/tcg-target.h | 20 +-\n tcg/i386/tcg-target.h | 36 +-\n tcg/tcg-gvec-desc.h | 49 +++\n tcg/tcg-op-gvec.h | 143 ++++++++\n tcg/tcg-op.h | 26 ++\n tcg/tcg-opc.h | 37 ++\n tcg/tcg.h | 34 ++\n accel/tcg/tcg-runtime-gvec.c | 255 +++++++++++++\n target/arm/translate-a64.c | 216 +++++++----\n tcg/aarch64/tcg-target.inc.c | 340 ++++++++++++++---\n tcg/i386/tcg-target.inc.c | 423 ++++++++++++++++++---\n tcg/tcg-op-gvec.c | 853 +++++++++++++++++++++++++++++++++++++++++++\n tcg/tcg-op.c | 234 ++++++++++++\n tcg/tcg.c | 77 +++-\n accel/tcg/Makefile.objs | 2 +-\n tcg/README | 46 +++\n 19 files changed, 2651 insertions(+), 168 deletions(-)\n create mode 100644 tcg/tcg-gvec-desc.h\n create mode 100644 tcg/tcg-op-gvec.h\n create mode 100644 accel/tcg/tcg-runtime-gvec.c\n create mode 100644 tcg/tcg-op-gvec.c"}