{"id":812281,"url":"http://patchwork.ozlabs.org/api/covers/812281/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/cover/1505122921-5534-1-git-send-email-bmeng.cn@gmail.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505122921-5534-1-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-09-11T09:41:50","name":"[v2,00/10] spi-nor: intel-spi: Various fixes and enhancements","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/cover/1505122921-5534-1-git-send-email-bmeng.cn@gmail.com/mbox/","series":[{"id":2464,"url":"http://patchwork.ozlabs.org/api/series/2464/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=2464","date":"2017-09-11T09:41:50","name":"spi-nor: intel-spi: Various fixes and enhancements","version":2,"mbox":"http://patchwork.ozlabs.org/series/2464/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/812281/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"This series does several bug fixes and clean ups against the intel-spi\nspi-nor driver, as well as enhancements to make the driver independent\non the underlying BIOS/bootloader.\n\nAt present the driver uses the HW sequencer for the read/write/erase on\nall supported platforms, read_reg/write_reg for BXT, and the SW sequencer\nfor read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW\nsequencer relies on some programmed register settings and hence creates\nunneeded dependencies with the underlying BIOS/bootloader. For example,\nthe driver unfortunately does not work as expected when booting from\nIntel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP\ndoes not set up some SPI controller settings to make the driver happy.\nNow such limitation has been removed with this series.\n\nChanges in v2:\n- Add stable kernel tags in the commit message (patch [03/10])\n- Fix typo of 'operatoin' (patch [10/10])\n- Add Mika Westerberg's 'Acked-by' tag\n\nBin Meng (10):\n spi-nor: intel-spi: Fix number of protected range registers for\n BYT/LPT\n spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycle\n spi-nor: intel-spi: Fix broken software sequencing codes\n spi-nor: intel-spi: Check transfer length in the HW/SW cycle\n spi-nor: intel-spi: Use SW sequencer for BYT/LPT\n spi-nor: intel-spi: Remove 'Atomic Cycle Sequence' in\n intel_spi_write()\n spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS\n spi-nor: intel-spi: Remove the unnecessary HSFSTS register RW\n spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi'\n spi-nor: intel-spi: Fall back to use SW sequencer to erase\n\n drivers/mtd/spi-nor/intel-spi.c | 209 +++++++++++++++++++++++++++++-----------\n 1 file changed, 151 insertions(+), 58 deletions(-)"}