{"id":810246,"url":"http://patchwork.ozlabs.org/api/covers/810246/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-05T18:26:52","name":"[0/4] iproc/xgene PCIe cap & whitespace cleanup","submitter":{"id":7584,"url":"http://patchwork.ozlabs.org/api/people/7584/?format=json","name":"Bjorn Helgaas","email":"bhelgaas@google.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com/mbox/","series":[{"id":1628,"url":"http://patchwork.ozlabs.org/api/series/1628/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=1628","date":"2017-09-05T18:26:52","name":"iproc/xgene PCIe cap & whitespace cleanup","version":1,"mbox":"http://patchwork.ozlabs.org/series/1628/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/810246/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org; dmarc=fail (p=reject dis=none)\n\theader.from=google.com","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmwD11J1Yz9sCZ\n\tfor ;\n\tWed, 6 Sep 2017 04:26:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752158AbdIES0z (ORCPT );\n\tTue, 5 Sep 2017 14:26:55 -0400","from mail.kernel.org ([198.145.29.99]:59522 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752108AbdIES0z (ORCPT );\n\tTue, 5 Sep 2017 14:26:55 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 7925021B64;\n\tTue, 5 Sep 2017 18:26:54 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 7925021B64","Subject":"[PATCH 0/4] iproc/xgene PCIe cap & whitespace cleanup","From":"Bjorn Helgaas ","To":"Jon Mason , Ray Jui ,\n\tOza Pawandeep , Tanmay Inamdar ,\n\tScott Branden ","Cc":"linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com","Date":"Tue, 05 Sep 2017 13:26:52 -0500","Message-ID":"<20170905181602.27030.65715.stgit@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"StGit/0.17.1-dirty","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Both iproc and xgene mask out PCI_EXP_RTCAP_CRSVIS (CRS Software\nVisibility). The point of these is to make them do it more\nconsistently.\n\nFor iproc, I renamed PCI_EXP_CAP to IPROC_PCI_EXP_CAP to make it\nobviously iproc-specific. Apparently the X-Gene PCIe capability is at\n0x40, at least for V1 root ports, so I added a corresponding\nXGENE_V1_PCI_EXP_CAP.\n\nX-Gene also defines PCIECORE_CTLANDSTATUS at 0x50, which is looks a\nlittle like the PCI_EXP_LNKCTL and PCI_EXP_LNKSTA registers which\nwould be at 0x50 in the PCIe capability, and PCIECORE_CTLANDSTATUS is\nused to determine whether the link is up. If this *were* actually\npart of a PCIe capability, I'd like to use the generic definitions.\n\nBut it's not clear from the code because PCIECORE_CTLANDSTATUS is used\nwith a simple xgene_pcie_readl(), while we read PCI_EXP_RTCTL using\npci_generic_config_read32(), so I'm not sure they're in the same\naddress space. So I didn't touch anything there.\n\nAlso, some trivial whitespace cleanup.\n\n---\n\nBjorn Helgaas (4):\n PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP\n PCI: iproc: Clean up whitespace\n PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset\n PCI: xgene: Clean up whitespace\n\n\n drivers/pci/host/pci-xgene.c | 41 +++----\n drivers/pci/host/pcie-iproc.c | 250 ++++++++++++++++++++---------------------\n 2 files changed, 144 insertions(+), 147 deletions(-)"}