{"id":2226895,"url":"http://patchwork.ozlabs.org/api/covers/2226895/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/cover/bmm.hhupmirk34.gcc.gcc-TEST.rearnsha.130.2.0@forge-stage.sourceware.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-22T19:07:15","name":"[v2,0/1] arm: avoid invalid shift in arm_canonicalize_comparison [PR122999]","submitter":{"id":92169,"url":"http://patchwork.ozlabs.org/api/people/92169/?format=json","name":"Richard Earnshaw via Sourceware Forge","email":"forge-bot+rearnsha@forge-stage.sourceware.org"},"mbox":"http://patchwork.ozlabs.org/project/gcc/cover/bmm.hhupmirk34.gcc.gcc-TEST.rearnsha.130.2.0@forge-stage.sourceware.org/mbox/","series":[{"id":501111,"url":"http://patchwork.ozlabs.org/api/series/501111/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501111","date":"2026-04-22T19:07:15","name":"arm: avoid invalid shift in arm_canonicalize_comparison [PR122999]","version":2,"mbox":"http://patchwork.ozlabs.org/series/501111/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2226895/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org","From":"Richard Earnshaw via Sourceware Forge\n ","Date":"Wed, 22 Apr 2026 19:07:15 +0000","Subject":"[PATCH v2 0/1] arm: avoid invalid shift in\n arm_canonicalize_comparison [PR122999]","To":"gcc-patches mailing list ","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/130","References":"\n ","In-Reply-To":"\n ","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"gcc-patches mailing list , rearnsha@arm.com","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Hi gcc-patches mailing list,\nRichard Earnshaw via Sourceware Forge has requested that the following forgejo pull request\nbe published on the mailing list.\n\nCreated on: 2025-12-05 16:36:37+00:00\nLatest update: 2025-12-05 17:32:58+00:00\nChanges: 0 changed files, 0 additions, 0 deletions\nHead revision: rearnsha/gcc-TEST ref refs/pull/130/head commit 550fab1f5100bff8773ec4b6838d51e3f41b3d5d\nBase revision: gcc/gcc-TEST ref trunk commit c48b55fa7764477008fbf187fadb352e3391a3f5 r16-5914-gc48b55fa776447\nMerge base: c48b55fa7764477008fbf187fadb352e3391a3f5\nFull diff url: https://forge.sourceware.org/gcc/gcc-TEST/pulls/130.diff\nDiscussion: https://forge.sourceware.org/gcc/gcc-TEST/pulls/130\nRequested Reviewers:\n\nThere was UB in arm_canonicalize_comparison if it is called with\nboth operands of type VOIDmode. Avoid this by first handling\nfloating-point types, then returning if we are left with anything\nother than an integer mode. For belt-and-braces also check that\nthe mode does not require a mask larger than HOST_WIDE_INT.\n\ngcc/ChangeLog:\n\n\tPR target/122999\n\t* config/arm/arm.cc (arm_canonicalize_comparison): Defer\n\tinitializing maxval until we know we are dealing with an\n\tinteger mode.\n\nThanks for taking the time to contribute to GCC!\n\nPlease be advised that https://forge.sourceware.org/ is currently a trial\nthat is being used by the GCC community to experiment with a new workflow\nbased on pull requests.\n\nPull requests sent here may be forgotten or ignored. Patches that you want to\npropose for inclusion in GCC should use the existing email-based workflow,\nsee https://gcc.gnu.org/contribute.html\n\n\nChanged files:\n\n\nRichard Earnshaw (1):\n arm: avoid invalid shift in arm_canonicalize_comparison [PR122999]\n\n\nRange-diff against v1:\n1: 068d8c06acb9 ! 1: 550fab1f5100 arm: avoid invalid shift in arm_canonicalize_comparison [PR122999]\n @@ Commit message\n * config/arm/arm.cc (arm_canonicalize_comparison): Defer\n initializing maxval until we know we are dealing with an\n integer mode.\n -\n - ## gcc/config/arm/arm.cc ##\n -@@ gcc/config/arm/arm.cc: arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,\n - if (mode == VOIDmode)\n - mode = GET_MODE (*op1);\n - \n -- maxval = (HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1)) - 1;\n --\n - /* For floating-point comparisons, prefer >= and > over <= and < since\n - the former are supported by VSEL on some architectures. Only do this\n - if both operands are registers. */\n -@@ gcc/config/arm/arm.cc: arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,\n - return;\n - }\n - \n -+ /* Everything below assumes an integer mode. */\n -+ if (GET_MODE_CLASS (mode) != MODE_INT\n -+ || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)\n -+ return;\n -+\n -+ maxval = (HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1)) - 1;\n -+\n - /* For DImode, we have GE/LT/GEU/LTU comparisons (with cmp/sbc). In\n - ARM mode we can also use cmp/cmpeq for GTU/LEU. GT/LE must be\n - either reversed or (for constant OP1) adjusted to GE/LT."}