{"id":2226868,"url":"http://patchwork.ozlabs.org/api/covers/2226868/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/cover/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-22T19:01:34","name":"[v2,00/14] arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts","submitter":{"id":92734,"url":"http://patchwork.ozlabs.org/api/people/92734/?format=json","name":"Christophe Lyon via Sourceware Forge","email":"forge-bot+clyon@forge-stage.sourceware.org"},"mbox":"http://patchwork.ozlabs.org/project/gcc/cover/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.0@forge-stage.sourceware.org/mbox/","series":[{"id":501104,"url":"http://patchwork.ozlabs.org/api/series/501104/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501104","date":"2026-04-22T19:01:35","name":"arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts","version":2,"mbox":"http://patchwork.ozlabs.org/series/501104/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2226868/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n 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t=1776884566; c=relaxed/simple;\n bh=ZTRgTyD/RKb9th0OOGpPkfITgtwoBqjZd6YJ41lvmCc=;\n h=From:Date:Subject:To:Message-ID;\n b=XvPa6vZKqS/eo8anS1Sq3DdixnoEOg0x1fj0h7FgQuwZr7UPNCylbto7XEyQ0bLRJn3f7P6ccnq8TzEKcKJ3i3EatHUwsc5nmYYT6DHmlW8/M45aglutWznKHZr8fabfYXcxvJydh4oYI6/UuGweMXbO2bu3YyYf0tuXDDz9d5Q=","ARC-Authentication-Results":"i=1; server2.sourceware.org","From":"Christophe Lyon via Sourceware Forge\n ","Date":"Wed, 22 Apr 2026 19:01:34 +0000","Subject":"[PATCH v2 00/14] arm: [MVE intrinsics] rework vpnot, vgetq_lane,\n vsetq_lane, vuninitialized and scalar shifts","To":"gcc-patches mailing list ","Cc":"sloosemore@baylibre.com","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/121","References":"\n <176235145474.426.7703351450807427807.batrachomyomachia.gcc.gcc-TEST.121.1.0@forge-stage.sourceware.org>","In-Reply-To":"\n <176235145474.426.7703351450807427807.batrachomyomachia.gcc.gcc-TEST.121.1.0@forge-stage.sourceware.org>","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"gcc-patches mailing list ,\n sloosemore@baylibre.com, clyon@gcc.gnu.org","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Hi gcc-patches mailing list,\nChristophe Lyon via Sourceware Forge has requested that the following forgejo pull request\nbe published on the mailing list.\n\nCreated on: 2025-11-05 13:54:48+00:00\nLatest update: 2025-11-17 16:33:24+00:00\nChanges: 49 changed files, 1787 additions, 794 deletions\nHead revision: clyon/gcc-TEST ref MVE-intrinsics-set-get-lane-vpnot-scalar-shifts2 commit 042aa77ce6e32b6ec2b5fe846b4f300e7eb83d34\nBase revision: gcc/gcc-TEST ref trunk commit 239535e9b0c4313072dda0ee1dcbd8ad8636a326 r16-4471-g239535e9b0c431\nMerge base: 239535e9b0c4313072dda0ee1dcbd8ad8636a326\nFull diff url: https://forge.sourceware.org/gcc/gcc-TEST/pulls/121.diff\nDiscussion: https://forge.sourceware.org/gcc/gcc-TEST/pulls/121\nRequested Reviewers:\n\nThis series implements the following MVE intrinsics using the \"new\" framework:\n\nvpnot\nvgetq_lane\nvsetq_lane\nasrl\nlsll\nuqrshll\nuqrshll_sat48\nsqrshrl\nsqrshrl_sat48\nsqshll\nsrshrl\nuqshll\nurshrl\nsqrshr\nsqshl\nsrshr\nuqrshl\nuqshl\nurshr\nvuninitialized\nIn the process:\n\n- also fix the patterns for MVE asrl lsll lsrl, adding support for out-of-range shift amounts\n- brings back a previous patch to fix support for fp16, needed by vgetq_lane\n- fixes the remaining vuninitialized instances\n\nSandra, could you please look at the doc change in patch 3/14 ?\n\n\nChanged files:\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl-various-ranges.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll-various-ranges.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f16.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f32.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f16.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f32.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-4-f16.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f16.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f32.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl_check_shift.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c\n- A: gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c\n- D: gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c\n- M: gcc/config/arm/arm-builtins.cc\n- M: gcc/config/arm/arm-mve-builtins-base.cc\n- M: gcc/config/arm/arm-mve-builtins-base.def\n- M: gcc/config/arm/arm-mve-builtins-base.h\n- M: gcc/config/arm/arm-mve-builtins-shapes.cc\n- M: gcc/config/arm/arm-mve-builtins-shapes.h\n- M: gcc/config/arm/arm-mve-builtins.cc\n- M: gcc/config/arm/arm-mve-builtins.h\n- M: gcc/config/arm/arm-opts.h\n- M: gcc/config/arm/arm.cc\n- M: gcc/config/arm/arm.md\n- M: gcc/config/arm/arm.opt\n- M: gcc/config/arm/arm_mve.h\n- M: gcc/config/arm/arm_mve_types.h\n- M: gcc/config/arm/constraints.md\n- M: gcc/config/arm/mve.md\n- M: gcc/config/arm/thumb2.md\n- M: gcc/doc/extend.texi\n- M: gcc/doc/sourcebuild.texi\n- M: gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c\n- M: gcc/testsuite/lib/target-supports.exp\n\n\nChristophe Lyon (14):\n arm: [MVE intrinsics] rework vpnot\n arm: [MVE intrinsics] Avoid warnings when floating-point is not\n supported [PR 117814]\n arm: doc: Update documentation on half-precision support\n arm: [MVE intrinsics] rework vgetq_lane vsetq_lane\n arm: fix MVE asrl lsll lsrl patterns [PR122216]\n arm: add support for out of range shift amount in MVE asrl and lsll\n [PR122216]\n arm: [MVE intrinsics] add scalar_s64_shift scalar_u64_shift shapes\n [PR122216]\n arm: [MVE intrinsics] rework asrl lsll [PR122216]\n arm: [MVE intrinsics] rework uqrshll uqrshll_sat48\n arm: [MVE intrinsics] rework sqrshrl sqrshrl_sat48\n arm: [MVE intrinsics] rework sqshll srshrl uqshll urshrl\n arm: [MVE intrinsics] rework sqrshr sqshl srshr uqrshl uqshl urshr\n arm: [MVE intrinsics] rework vuninitialized\n arm: [MVE intrinsics] remove __ARM_mve_coerce in arm_mve.h\n\n gcc/config/arm/arm-builtins.cc | 4 +-\n gcc/config/arm/arm-mve-builtins-base.cc | 205 ++++++\n gcc/config/arm/arm-mve-builtins-base.def | 23 +\n gcc/config/arm/arm-mve-builtins-base.h | 19 +\n gcc/config/arm/arm-mve-builtins-shapes.cc | 289 +++++++-\n gcc/config/arm/arm-mve-builtins-shapes.h | 12 +\n gcc/config/arm/arm-mve-builtins.cc | 32 +-\n gcc/config/arm/arm-mve-builtins.h | 1 +\n gcc/config/arm/arm-opts.h | 1 +\n gcc/config/arm/arm.cc | 14 +-\n gcc/config/arm/arm.md | 17 +-\n gcc/config/arm/arm.opt | 2 +-\n gcc/config/arm/arm_mve.h | 660 +-----------------\n gcc/config/arm/arm_mve_types.h | 2 -\n gcc/config/arm/constraints.md | 5 +-\n gcc/config/arm/mve.md | 212 +++++-\n gcc/config/arm/thumb2.md | 24 -\n gcc/doc/extend.texi | 118 ++--\n gcc/doc/sourcebuild.texi | 6 +\n .../arm/mve/general-c++/nomve_fp_1.c | 2 +-\n .../gcc.target/arm/fp16-compile-none-1.c | 7 -\n .../arm/mve/intrinsics/asrl-various-ranges.c | 161 +++++\n .../arm/mve/intrinsics/lsll-various-ranges.c | 160 +++++\n .../arm/mve/intrinsics/pr117814-2-f16.c | 30 +\n .../arm/mve/intrinsics/pr117814-2-f32.c | 30 +\n .../arm/mve/intrinsics/pr117814-3-f16.c | 21 +\n .../arm/mve/intrinsics/pr117814-3-f32.c | 21 +\n .../arm/mve/intrinsics/pr117814-4-f16.c | 23 +\n .../arm/mve/intrinsics/pr117814-f16.c | 22 +\n .../arm/mve/intrinsics/pr117814-f32.c | 22 +\n .../arm/mve/intrinsics/sqshl_check_shift.c | 24 +\n .../arm/mve/intrinsics/sqshll_check_shift.c | 24 +\n .../arm/mve/intrinsics/srshr_check_shift.c | 24 +\n .../arm/mve/intrinsics/srshrl_check_shift.c | 24 +\n .../arm/mve/intrinsics/uqshl_check_shift.c | 24 +\n .../arm/mve/intrinsics/uqshll_check_shift.c | 24 +\n .../arm/mve/intrinsics/urshr_check_shift.c | 24 +\n .../arm/mve/intrinsics/urshrl_check_shift.c | 24 +\n .../mve/intrinsics/vsetq_lane_f16_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_f32_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_s16_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_s32_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_s64_bounds.c | 19 +\n .../arm/mve/intrinsics/vsetq_lane_s8_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_u16_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_u32_bounds.c | 19 +\n .../mve/intrinsics/vsetq_lane_u64_bounds.c | 19 +\n .../arm/mve/intrinsics/vsetq_lane_u8_bounds.c | 19 +\n gcc/testsuite/lib/target-supports.exp | 54 ++\n 49 files changed, 1787 insertions(+), 794 deletions(-)\n delete mode 100644 gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl-various-ranges.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll-various-ranges.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-2-f32.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-3-f32.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-4-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f16.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/pr117814-f32.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64_bounds.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8_bounds.c\n\nRange-diff against v1:\n 1: 3ef1ae2e8fb3 = 1: 9426c473bf85 arm: [MVE intrinsics] rework vpnot\n 2: 63bd69b862b1 = 2: 84550d5c0a2f arm: [MVE intrinsics] Avoid warnings when floating-point is not supported [PR 117814]\n 3: 06a424c3038f ! 3: 360badda7fb0 arm: doc: Update documentation on half-precision support\n @@ Commit message\n \n gcc/ChangeLog:\n * doc/extend.texi (Half-precision Floating-point): __fp16 is now\n - always available on arm. More x86 paragraph closer to the rest of\n - the x86 information.\n + always available on arm. Move x86 paragraph closer to the rest of\n + the x86 information, and make it use present tense.\n \n ## gcc/doc/extend.texi ##\n @@ gcc/doc/extend.texi: typedef _Complex float __attribute__((mode(IC))) _Complex_ibm128;\n @@ gcc/doc/extend.texi: instructions. In cases where hardware support is not speci\n +You must choose one of the formats and use it consistently in your\n +program.\n +\n -+GCC only supports the 'alternative' format on implementations that\n -+support it in hardware; there is no support for conversions to and\n -+from this format using library functions. Furthermore, you cannot\n ++GCC only supports the @samp{alternative} format on implementations\n ++that support it in hardware; there is no support for conversions to\n ++and from this format using library functions. Furthermore, you cannot\n +link together code compiled with one format and code compiled for the\n +other. GCC also supports the @option{-mfp16-format=none} option,\n +which disables all support for half-precision floating-point types.\n @@ gcc/doc/extend.texi: instructions. In cases where hardware support is not speci\n +The Arm architecture extension @code{FEAT_FP16} (enabled, for example,\n +with @option{-march=armv8.2-a+fp16}, or\n +@option{-march=armv8.1-m.main+mve.fp}) defines data processing\n -+instructions that only support the 'ieee' format. The compiler will\n -+reject attempts to use the 'alternative' format when this architecture\n -+extension is enabled.\n ++instructions that only support the @samp{ieee} format. The compiler\n ++rejects attempts to use the @samp{alternative} format when this\n ++architecture extension is enabled.\n +\n -+Note that the ACLE has deprecated use of the 'alternative' format and\n -+recommends that only the 'ieee' format be used.\n ++Note that the ACLE has deprecated use of the @samp{alternative} format\n ++and recommends that only the @samp{ieee} format be used.\n +\n +The default is to compile with @option{-mfp16-format=ieee}.\n +\n @@ gcc/doc/extend.texi: instructions. In cases where hardware support is not speci\n +\n +@item\n +@code{_Float16}, which is defined by ISO/IEC TS 18661-3:2015. This is\n -+only defined when the format selected is 'ieee'.\n ++only defined when the format selected is @samp{ieee}.\n +@end itemize\n +\n +The GCC port for AArch64 only supports the IEEE 754-2008 format, and\n @@ gcc/doc/extend.texi: instructions. In cases where hardware support is not speci\n +\n \n On x86 targets with SSE2 enabled, without @option{-mavx512fp16},\n - all operations will be emulated by software emulation and the @code{float}\n +-all operations will be emulated by software emulation and the @code{float}\n ++all operations are emulated by software emulation and the @code{float}\n + instructions. The default behavior for @code{FLT_EVAL_METHOD} is to keep the\n + intermediate result of the operation as 32-bit precision. This may lead to\n + inconsistent behavior between software emulation and AVX512-FP16 instructions.\n +-Using @option{-fexcess-precision=16} will force round back after each operation.\n ++Using @option{-fexcess-precision=16} forces round back after each operation.\n + \n +-Using @option{-mavx512fp16} will generate AVX512-FP16 instructions instead of\n ++Using @option{-mavx512fp16} generates AVX512-FP16 instructions instead of\n + software emulation. The default behavior of @code{FLT_EVAL_METHOD} is to round\n + after each operation. The same is true with @option{-fexcess-precision=standard}\n + and @option{-mfpmath=sse}. If there is no @option{-mfpmath=sse},\n 4: 027aecaefb9a = 4: 213409068981 arm: [MVE intrinsics] rework vgetq_lane vsetq_lane\n 5: 82d71cf581b6 = 5: 02e88f11462c arm: fix MVE asrl lsll lsrl patterns [PR122216]\n 6: 2dbbad09e70c = 6: 41c9e3192df9 arm: add support for out of range shift amount in MVE asrl and lsll [PR122216]\n 7: c35f8b1a42b5 = 7: 2b8088fba6ee arm: [MVE intrinsics] add scalar_s64_shift scalar_u64_shift shapes [PR122216]\n 8: 9220122114d0 = 8: 67b6e85cf717 arm: [MVE intrinsics] rework asrl lsll [PR122216]\n 9: 23cbd0c241f3 = 9: ba3b31aaa48e arm: [MVE intrinsics] rework uqrshll uqrshll_sat48\n10: bcdf10919413 = 10: 65d776a09a8f arm: [MVE intrinsics] rework sqrshrl sqrshrl_sat48\n11: 3070afd62ec6 = 11: cd827f2f2618 arm: [MVE intrinsics] rework sqshll srshrl uqshll urshrl\n12: 4012aed6bf77 = 12: 6232c033bf55 arm: [MVE intrinsics] rework sqrshr sqshl srshr uqrshl uqshl urshr\n13: 200d40683f98 = 13: 171997108826 arm: [MVE intrinsics] rework vuninitialized\n14: 5e79d7cfcafa = 14: 042aa77ce6e3 arm: [MVE intrinsics] remove __ARM_mve_coerce in arm_mve.h"}