{"id":2225992,"url":"http://patchwork.ozlabs.org/api/covers/2225992/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/1776821127-234830-1-git-send-email-shawn.lin@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1776821127-234830-1-git-send-email-shawn.lin@rock-chips.com>","list_archive_url":null,"date":"2026-04-22T01:25:24","name":"[v3,0/3] Add Devres managed IRQ vectors allocation","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/people/66993/?format=json","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/1776821127-234830-1-git-send-email-shawn.lin@rock-chips.com/mbox/","series":[{"id":500907,"url":"http://patchwork.ozlabs.org/api/series/500907/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500907","date":"2026-04-22T01:25:24","name":"Add Devres managed IRQ vectors allocation","version":3,"mbox":"http://patchwork.ozlabs.org/series/500907/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2225992/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=X6G52eu+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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t=1776821159; c=relaxed/simple;\n\tbh=FapvHKhHuHGEUhwmMlxlgK5wFbzLcR/YVtjzNQfj/y0=;\n\th=From:To:Cc:Subject:Date:Message-Id;\n b=r5SWx8r7dwAtuhjaX2zOUL1Pvg1uCX5vzU+1FWH9G5niSSq78tapy4y946IbLtTcFmW9Q33EaMEX1AGrjcnlbUTys3fnd2ghNPaJCmx5rvyGKYRoEkCnXLLMI7ECZY/FOfg9uDM8n98kAEnBYw+e71M61zFj2LV1R2awvqhqlHA=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com;\n spf=pass smtp.mailfrom=rock-chips.com;\n dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=X6G52eu+; arc=none smtp.client-ip=45.254.49.220","From":"Shawn Lin ","To":"Bjorn Helgaas ","Cc":"Nirmal Patel ,\n\tJonathan Derrick ,\n\tKurt Schwemmer ,\n\tLogan Gunthorpe ,\n\tPhilipp Stanner ,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin ","Subject":"[PATCH v3 0/3] Add Devres managed IRQ vectors allocation","Date":"Wed, 22 Apr 2026 09:25:24 +0800","Message-Id":"<1776821127-234830-1-git-send-email-shawn.lin@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","X-HM-Tid":"0a9db2cb0d0109cckunm4d4f8bca15dec9","X-HM-MType":"1","X-HM-Spam-Status":"e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCSBoZVk1DHU5LGUsZHktPSVYVFAkWGhdVEwETFh\n\toSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSktLVU\n\tpCS0tZBg++","DKIM-Signature":"a=rsa-sha256;\n\tb=X6G52eu+bmZwEpHMN4wp3voEa+0qHL+/D8tcu9+vqszzDrM/7qwpIEfeMrPEXLSET6qqv7n07JIhXq71pm2/CHz538YiahhyLEUR5mVrNLT0dis3kXA4lEDSUTFPXkceciIVE9wZB6+dZqhKq+3RXSu9eBrdCRIntxrdfFjxPPc=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=1f90EMBDsB8nqVk5sZbeh+FS5qzfGZ/gu7kALfL7AvU=;\n\th=date:mime-version:subject:message-id:from;","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""},"content":"There is a long-standing design issue in the PCI/MSI subsystem where the\nimplicit, automatic management of IRQ vectors by the devres framework\nconflicts with explicit driver cleanup, creating ambiguity and potential\nresource management bugs.\n\nHistorically, pcim_enable_device() not only manages standard PCI resources\n(BARs) via devres but also implicitly triggers automatic IRQ vector management\nwhen calling pci_alloc_irq_vectors[_affinity], because pcim_enable_device()\nsets is_managed flag, thus pcim_msi_release() will register a cleanup action.\n\nThis creates an ambiguous ownership model. Many drivers follow a pattern of:\n1. Calling pci_alloc_irq_vectors() to allocate interrupts.\n2. Also calling pci_free_irq_vectors() in their error paths or remove routines.\n\nWhen such a driver also uses pcim_enable_device(), the devres framework may\nattempt to free the IRQ vectors a second time upon device release, leading to\na double-free. Analysis of the tree shows this hazardous pattern exists widely,\nwhile 35 other drivers correctly rely solely on the implicit cleanup.\n\nThis series introduces new managed APIs: pcim_alloc_irq_vectors()and\npcim_alloc_irq_vectors_affinity(). Drivers that wish to have devres-managed IRQ\nvectors should use these functions. They are currently the same as non-devres\nmanaged version. In the short term, the series converts two drivers within the\nPCI subsystem to use the new APIs. The long-term goal is to convert all other\ndrivers which wish to use these managed functions, and finally to remove the\nproblematic hybrid management pattern from pcim_enable_device() and\npcim_setup_msi_release() entirely.\n\n\nChanges in v3:\n- Rework the commit message and function doc (Philipp)\n- Remove setting is_msi_managed flag from new APIs (Philipp)\n\nChanges in v2:\n- Rebase\n- Introduce patches only for PCI subsystem to convert the API\n\nShawn Lin (3):\n PCI/MSI: Add Devres managed IRQ vectors allocation\n PCI: switchtec: Replace pci_alloc_irq_vectors() with\n pcim_alloc_irq_vectors()\n PCI: vmd: Replace pci_alloc_irq_vectors() with\n pcim_alloc_irq_vectors()\n\n drivers/pci/controller/vmd.c | 4 ++--\n drivers/pci/msi/api.c | 51 ++++++++++++++++++++++++++++++++++++++++++\n drivers/pci/switch/switchtec.c | 6 ++---\n include/linux/pci.h | 22 ++++++++++++++++++\n 4 files changed, 78 insertions(+), 5 deletions(-)"}