{"id":2224161,"url":"http://patchwork.ozlabs.org/api/covers/2224161/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/cover/20260417022104.3973576-1-ycliang@andestech.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417022104.3973576-1-ycliang@andestech.com>","list_archive_url":null,"date":"2026-04-17T02:20:56","name":"[0/8] spi: atcspi200: Modernize driver and add spi-mem + data merge support","submitter":{"id":79234,"url":"http://patchwork.ozlabs.org/api/people/79234/?format=json","name":"Leo Yu-Chi Liang","email":"ycliang@andestech.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/cover/20260417022104.3973576-1-ycliang@andestech.com/mbox/","series":[{"id":500221,"url":"http://patchwork.ozlabs.org/api/series/500221/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=500221","date":"2026-04-17T02:20:56","name":"spi: atcspi200: Modernize driver and add spi-mem + data merge support","version":1,"mbox":"http://patchwork.ozlabs.org/series/500221/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2224161/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Fri, 17 Apr 2026 04:21:29 +0200 (CEST)","from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 4672183EEF\n for ; Fri, 17 Apr 2026 04:21:25 +0200 (CEST)","from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 63H2LAa3015783;\n Fri, 17 Apr 2026 10:21:10 +0800 (+08)\n (envelope-from ycliang@andestech.com)","from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 17 Apr\n 2026 10:21:10 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2","From":"Leo Yu-Chi Liang ","To":"","CC":"Tom Rini , Vignesh R , \"Takahiro\n Kuwano\" , Jagan Teki\n , ","Subject":"[PATCH 0/8] spi: atcspi200: Modernize driver and add spi-mem + data\n merge support","Date":"Fri, 17 Apr 2026 10:20:56 +0800","Message-ID":"<20260417022104.3973576-1-ycliang@andestech.com>","X-Mailer":"git-send-email 2.34.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.0.15.183]","X-ClientProxiedBy":"ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)","X-DKIM-Results":"atcpcs34.andestech.com; dkim=none;","X-DNSRBL":"","X-MAIL":"Atcsqr.andestech.com 63H2LAa3015783","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"This series modernizes the Andes ATCSPI200 SPI controller driver and\nadds two new features: spi-mem framework support (including dual/quad\nmodes) and an optional 4-byte data merge mode for higher throughput on\naligned transfers.\n\nPatches 1-4 are cleanups and fixes with no intended functional change\nto existing behavior:\n\n 1. Replace volatile struct register access with readl()/writel() +\n offset defines, convert bit macros to BIT()/GENMASK()/FIELD_PREP(),\n modernize DT parsing (dev_read_u32_default, dev_remap_addr),\n rename struct nds_spi_slave to atcspi200_priv, and fix coding\n style throughout.\n 2. Improve clock configuration: add sensible fallbacks for clock\n source and max frequency, honor spi-max-frequency from DT, use a\n round-up divider that picks the closest frequency not exceeding\n the target, and stop clobbering clock settings on every stop().\n 3. Replace manual busy-wait counters with wait_for_bit_le32() and\n get_timer() based timeouts so the driver benefits from watchdog\n handling and time-based (rather than iteration-based) limits.\n 4. Remove a duplicate atcspi200_hw_stop() call after the transfer\n loop and simplify the CHUNK_SIZE=1 transfer logic that had\n accumulated dead variables. Also includes a Fixes: tag for the\n duplicate-stop issue.\n\nPatches 5-6 add new functionality:\n\n 5. Wire up spi_controller_mem_ops so the driver can service the\n spi-mem framework with proper cmd/addr/dummy/data phase handling\n and single/dual/quad bus widths. A shared atcspi200_pio_transfer()\n helper is used by both the spi-mem and legacy xfer paths.\n 6. Add CONFIG_ATCSPI200_SPI_DATA_MERGE. When enabled and the\n transfer is 4-byte aligned, the driver uses 32-bit FIFO accesses\n (one u32 per register access instead of one byte) for a\n meaningful throughput improvement. Data merge is enabled/disabled\n dynamically per transfer based on alignment.\n\nPatches 7-8 are consumers of the new support:\n\n 7. Add quad-mode (1-4-4) read and page-program fixups for Macronix\n MX25U1635E and MX25U25635F, which do not advertise their quad\n capabilities correctly via SFDP.\n 8. Enable CONFIG_ATCSPI200_SPI_DATA_MERGE in all AE350 defconfig\n variants.\n\nTested on AE350 with MX25U1635E and MX25U25635F flash in 1-1-1, 1-1-4,\nand 1-4-4 modes, with and without data merge.\n\nLeo Yu-Chi Liang (8):\n spi: atcspi200: Clean up register access, macros, naming, DT parsing,\n and style\n spi: atcspi200: Improve clock configuration and divider logic\n spi: atcspi200: Use proper timeout handling for busy-wait loops\n spi: atcspi200: Fix double stop call and simplify transfer loop\n spi: atcspi200: Add spi-mem framework support\n spi: atcspi200: Add data merge mode support\n mtd: spi-nor: Add Macronix MX25U quad-mode fixups\n configs: ae350: Enable ATCSPI200 data merge mode\n\n configs/ae350_rv32_defconfig | 1 +\n configs/ae350_rv32_falcon_defconfig | 1 +\n configs/ae350_rv32_falcon_xip_defconfig | 1 +\n configs/ae350_rv32_spl_defconfig | 1 +\n configs/ae350_rv32_spl_xip_defconfig | 1 +\n configs/ae350_rv32_xip_defconfig | 1 +\n configs/ae350_rv64_defconfig | 1 +\n configs/ae350_rv64_falcon_defconfig | 1 +\n configs/ae350_rv64_falcon_xip_defconfig | 1 +\n configs/ae350_rv64_spl_defconfig | 1 +\n configs/ae350_rv64_spl_xip_defconfig | 1 +\n configs/ae350_rv64_xip_defconfig | 1 +\n drivers/mtd/spi/spi-nor-core.c | 25 +-\n drivers/spi/Kconfig | 9 +\n drivers/spi/atcspi200_spi.c | 658 ++++++++++++++----------\n 15 files changed, 436 insertions(+), 268 deletions(-)"}