{"id":2224043,"url":"http://patchwork.ozlabs.org/api/covers/2224043/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260416165353.589569-1-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260416165353.589569-1-peter.maydell@linaro.org>","list_archive_url":null,"date":"2026-04-16T16:53:50","name":"[v2,0/3] target/arm: Allow aarch64=off for TCG","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260416165353.589569-1-peter.maydell@linaro.org/mbox/","series":[{"id":500185,"url":"http://patchwork.ozlabs.org/api/series/500185/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500185","date":"2026-04-16T16:53:50","name":"target/arm: Allow aarch64=off for TCG","version":2,"mbox":"http://patchwork.ozlabs.org/series/500185/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2224043/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=efo5zqTF;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxPJP48P9z1yG9\n\tfor ; Fri, 17 Apr 2026 02:55:00 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDPye-00068W-Eg; Thu, 16 Apr 2026 12:54:04 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wDPyc-000681-5o\n for qemu-devel@nongnu.org; Thu, 16 Apr 2026 12:54:03 -0400","from mail-wm1-x330.google.com ([2a00:1450:4864:20::330])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wDPyZ-0007Wc-LS\n for qemu-devel@nongnu.org; Thu, 16 Apr 2026 12:54:01 -0400","by mail-wm1-x330.google.com with SMTP id\n 5b1f17b1804b1-4852a9c6309so75965655e9.0\n for ; Thu, 16 Apr 2026 09:53:59 -0700 (PDT)","from lanath.. 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This is useful because\ncurrently if you want a 32-bit TCG CPU you're limited to either\n'max' in qemu-system-arm or else the old v7-only CPUs like a15.\n\nI sent out v1 back in October last year. The main changes\nhere are:\n - as I said we ought to do in a follow up to those patches\n https://lore.kernel.org/qemu-devel/CAFEAcA9KeO2r+jNont_2Jpvi5MgViH3nXO7TcbANe+3nS_PF-A@mail.gmail.com/\n I've switched to only clearing the AArch64 ID regs with\n TCG; we leave the KVM aarch64=off behaviour alone. (Clearing\n the regs didn't break KVM, but did leave us in the odd\n situation that QEMU and KVM didn't have the same idea about\n what the ID reg values were, which seems like it might lead\n to subtle problems later.)\n - I've added a simple functional test which boots one of\n the kernels we use for a 32-bit functional test using\n qemu-system-aarch64 and -cpu max,aarch64=off\n\nI also made a tiny tweak to the docs wording.\n\nPatches 1 and 3 need review.\n\nthanks\n-- PMM\n\nPeter Maydell (3):\n target/arm: Clear AArch64 ID regs from ARMISARegisters if AArch64\n disabled\n target/arm: Allow 'aarch64=off' to be set for TCG CPUs\n tests/functional/aarch64: Add basic test of TCG aarch64=off\n\n docs/system/arm/cpu-features.rst | 10 +--\n target/arm/cpu-features.h | 5 ++\n target/arm/cpu.c | 71 +++++++++++++++++--\n target/arm/cpu.h | 3 +-\n tests/functional/aarch64/meson.build | 1 +\n .../aarch64/test_virt_aarch64_off.py | 37 ++++++++++\n tests/qtest/arm-cpu-features.c | 8 +--\n 7 files changed, 120 insertions(+), 15 deletions(-)\n create mode 100755 tests/functional/aarch64/test_virt_aarch64_off.py"}