{"id":2223385,"url":"http://patchwork.ozlabs.org/api/covers/2223385/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>","list_archive_url":null,"date":"2026-04-15T08:01:46","name":"[v4,0/7] PCI: intel-gw: Fixes to make the driver working again","submitter":{"id":72238,"url":"http://patchwork.ozlabs.org/api/people/72238/?format=json","name":"Florian Eckert","email":"fe@dev.tdt.de"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de/mbox/","series":[{"id":499942,"url":"http://patchwork.ozlabs.org/api/series/499942/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499942","date":"2026-04-15T08:01:47","name":"PCI: intel-gw: Fixes to make the driver working again","version":4,"mbox":"http://patchwork.ozlabs.org/series/499942/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2223385/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=temperror header.d=dev.tdt.de header.i=@dev.tdt.de header.a=rsa-sha256\n header.s=z1-selector1 header.b=FwI/FfcL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-B4-Tracking":"v=1; b=H4sIAOpF32kC/3XM0Q6CIBiG4VtpHIf7AQXtqPtoHaj8KFtTB4xqz\n nsPPalsHX7f9rwz8egsenI6zMRhtN6OQxr58UDavh46pFanTThwCYIpOrU2fUPAG+3utIAKOGP\n CVMhIMpNDYx9b73JNu7c+jO655SNb33+lyChQZZAJxWWtc3PWGLOgQ6aRrKnIP7iAPeeJl40GJ\n aSqeVX+cPHmObA9F4lL0QCUbdGohn/xZVleheIr9CkBAAA=","X-Change-ID":"20260317-pcie-intel-gw-50902113f9e1","To":"Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Johan Hovold ,\n Sajid Dalvi , Ajay Agarwal ,\n Krzysztof Kozlowski , Conor Dooley ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Florian Eckert ,\n\tEckert.Florian@googlemail.com, ms@dev.tdt.de","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776240111; l=2895;\n i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id;\n bh=OCOPR7qYQ86i9LLtRG/G6UnUj18IRRl3gvRDhTM5HQ8=;\n b=3sl2U8fR2DoW0OCmRmD9z/jZMuL/tF//nC02A8Et7Uhw5TbUNquUfUuScAbP4un+8LZpnKbUv\n F/XaveZPSKKAOvOnVdJUdmLgH95h3QeYpameqF4V4JWXXJSFXa9ez5M","X-Developer-Key":"i=fe@dev.tdt.de; a=ed25519;\n pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk=","X-purgate-type":"clean","X-purgate":"clean","X-purgate-ID":"151534::1776240113-5615A19A-7DF273C6/0/0"},"content":"This series fixes and improve the 'intel-gw' driver to work again with\nthe current dwc pcie framework. The following changes are:\n\n* Move interrupt 'enable' to its own function to improve readability,\n and add additional register writes just as the Maxlinear kernel does in\n their SDK.\n* Enable clock for the PHY before PHY init call.\n* Add missing 'start_link' callback. That was added to the PCIe dwc\n framework.\n* Move ATU base address assignment to the probe function and also add the\n the possibility to read it from the devicetree by dwc core.\n* Update devicetree documentation for intel-gw-pcie.yaml\n* Remove unused preprocessor define.\n* Mark driver as orphaned as the maitainer's email no longer works\n\nSigned-off-by: Florian Eckert \n---\nChanges in v4:\n- Add 'atu' to the end of the resource definition to ensure backwords\n compatibility.\n- Updated the commit description to explain why the MaxLinear SDK is used\n as a reference.\n- Remove 'Rahul Tanwar ' out of the loop, as the email\n address is no longer valid and is being rejected.\n- Link to v3: https://lore.kernel.org/r/20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de\n\nChanges in v3:\n- Update commit messages.\n- Correct the sample code for dt bindings by adding the missing quotation\n marks. Add 'minItems: 3' to avoid ABI issues.\n- Move driver atu base assignment to probe function and keep backward\n compatibility.\n- Link to v2: https://lore.kernel.org/r/20260330-pcie-intel-gw-v2-0-8bd07367a298@dev.tdt.de\n\nChanges in v2:\n- Added additional information to the commit descriptions\n- Add additional patch to mark driver as orphaned as the maintainer's\n email no longer works.\n- Fix wrong error path for enable clock before phy init.\n- Add new patch to update the devicetree documentation for the 'atu'\n resource\n- Add additional recipients responsible for documenting the dervicetree\n bindings.\n- Link to v1: https://lore.kernel.org/r/20260317-pcie-intel-gw-v1-0-7fe13726ad4f@dev.tdt.de\n\n---\nFlorian Eckert (7):\n MAINTAINERS: Remove bouncing intel-gw maintainer\n PCI: intel-gw: Remove unused define\n PCI: intel-gw: Move interrupt enable to own function\n PCI: intel-gw: Enable clock before phy init\n PCI: intel-gw: Add start_link callback function\n PCI: intel-gw: Move driver atu base assignment to probe function\n dt-bindings: PCI: intel,lgm-pcie: Add atu resource\n\n .../devicetree/bindings/pci/intel-gw-pcie.yaml | 8 ++-\n MAINTAINERS | 3 +-\n drivers/pci/controller/dwc/pcie-intel-gw.c | 73 +++++++++++++++-------\n 3 files changed, 57 insertions(+), 27 deletions(-)\n---\nbase-commit: 028ef9c96e96197026887c0f092424679298aae8\nchange-id: 20260317-pcie-intel-gw-50902113f9e1\n\nBest regards,"}