{"id":2223157,"url":"http://patchwork.ozlabs.org/api/covers/2223157/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260414155433.483186-1-magnuskulke@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-14T15:54:24","name":"[v4,0/9] Support QEMU cpu models in MSHV accelerator","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/?format=json","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260414155433.483186-1-magnuskulke@linux.microsoft.com/mbox/","series":[{"id":499862,"url":"http://patchwork.ozlabs.org/api/series/499862/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499862","date":"2026-04-14T15:54:24","name":"Support QEMU cpu models in MSHV accelerator","version":4,"mbox":"http://patchwork.ozlabs.org/series/499862/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2223157/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=WDSBcvTe;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fw84G3hwtz1xtJ\n\tfor ; Wed, 15 Apr 2026 01:55:10 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCg68-0004AD-2r; Tue, 14 Apr 2026 11:54:44 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCg66-0004A0-V0\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 11:54:42 -0400","from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1wCg65-0000D9-9j\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 11:54:42 -0400","from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 6BFC120B6F01;\n Tue, 14 Apr 2026 08:54:37 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.11.0 linux.microsoft.com 6BFC120B6F01","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776182079;\n bh=lIPPzyrl6JxMQVf94O6Y2eckUBAystmbLuQP3CteQ7s=;\n h=From:To:Cc:Subject:Date:From;\n b=WDSBcvTeOIpQ3RJTfdbZ1lnhGW61Li03VAHMsOMetToGlxeEzgF8KE//SdS4Ix4NX\n YMFloC56PSm8DLLn7WzIgcFUO6++RIMB5Rycnd3TWSluxkz7E+zlQTZdmND+Ws4RTZ\n aQVQXwnxc75UaEXAJCCbwRxAnX1Y+0ehvWB1QA2M=","From":"Magnus Kulke ","To":"qemu-devel@nongnu.org","Cc":"Wei Liu , Wei Liu ,\n Magnus Kulke ,\n Magnus Kulke , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v4 0/9] Support QEMU cpu models in MSHV accelerator","Date":"Tue, 14 Apr 2026 17:54:24 +0200","Message-Id":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","X-Mailer":"git-send-email 2.34.1","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Hey all,\n\nIn the current MSHV accelerator code passing CPU features via the -cpu\nflag doesn't work as intended yet. When using the MSHV hypervisor we\neither silently discard the specified model/features and leave it up\nto the hypervisor to provide a sensible set of features or if the user\nselects -cpu host, the hypervisor might refuse to create a partition.\n\nThis changeset introduces a more comprehensive support for passing\ndesired guest cpu features to the hypervisor. It's also a prerequisite\nfor Live Migration support.\n\nChanges since v3:\n\n- Rebased onto current master\n\nChanges since v2:\n\n- move disabling of la57 to arch specific code\n- assert MSHV_NUM_CPU_FEATURES_BANKS == 2\n- dropped QEMU_PACKED changes to hv headers (address in individal patch)\n\nChanges since v1:\n\n- query hypervisor for supported processor features instead of the host OS\n- disable la57 (5 level page tables)\n\nbest,\n\nmagnus\n\nMagnus Kulke (9):\n accel/mshv: use mshv_create_partition_v2 payload\n target/i386/mshv: fix cpuid propagation bug\n target/i386/mshv: fix various cpuid traversal bugs\n target/i386/mshv: change cpuid mask to UINT32_MAX\n target/i386/mshv: set cpu model name on -cpu host\n target/i386: query mshv accel for supported cpuids\n target/i386/mshv: populate xsave area offsets\n target/i386/mshv: filter out CET bits in cpuid\n accel/mshv: disable la57 (5lvl paging)\n\n accel/mshv/mshv-all.c | 78 ++++++++++-\n include/hw/hyperv/hvgdk_mini.h | 2 +\n include/hw/hyperv/hvhdk.h | 195 +++++++++++++++++++++++++++\n include/system/mshv.h | 3 +\n include/system/mshv_int.h | 2 +\n target/i386/cpu.c | 8 ++\n target/i386/mshv/mshv-cpu.c | 233 +++++++++++++++++++++++++++------\n 7 files changed, 472 insertions(+), 49 deletions(-)"}