{"id":2222991,"url":"http://patchwork.ozlabs.org/api/covers/2222991/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260414080025.3005916-1-jamin_lin@aspeedtech.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414080025.3005916-1-jamin_lin@aspeedtech.com>","list_archive_url":null,"date":"2026-04-14T08:00:26","name":"[v2,00/17] hw/usb/ehci: Add 64-bit descriptor addressing support","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/?format=json","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260414080025.3005916-1-jamin_lin@aspeedtech.com/mbox/","series":[{"id":499795,"url":"http://patchwork.ozlabs.org/api/series/499795/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499795","date":"2026-04-14T08:00:26","name":"hw/usb/ehci: Add 64-bit descriptor addressing support","version":2,"mbox":"http://patchwork.ozlabs.org/series/499795/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2222991/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=IJXUd137;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-Exchange-RoutingPolicyChecked":"\n s62Tsq3SW03EWEHj3rqODoOr1cNet/zcmjtq3E5nEtjvf/a0V4u7IckrHp1ixUIQ1dQ/mByn35E3IdHZtCxbhnsKe1Ux0FiF+YLIFCTZkHI0D8WIXgSLAKjC2dBu7nN2wwxwmqnx+Q7EV6+R9UoVn86p029ciB3qj+aEHt66hyvS+7nkrFAjY0m5Dn+Co7GRzndKBzrazuP21IE6ySq60WN22norgW7uBlJPjvqGJbJJ35SxfEfvNJFCfUy4yKOKtTmEDuk0SxQ8XZseoVscBrBuc0ZWO7VAJZffYiMZlTzZI1mfmuZv5OFSLPH9ebZtPtMXEFdhF3H48TjoPtnZYw==","X-OriginatorOrg":"aspeedtech.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"TYPPR06MB8206.apcprd06.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 4c56d756-c20e-4318-5b59-08de99fbe36d","X-MS-Exchange-CrossTenant-originalarrivaltime":"14 Apr 2026 08:00:26.4030 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"43d4aa98-e35b-4575-8939-080e90d5a249","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n n8feH+o0eGAkxfUk+s9CicyQHG8hI4YFSYY9uq0F43unxeP/V252NzJd7vpKKZhp5/m5qUUe5tePHH/VWEL7PJU5XxqG40ZE84Jbz0XBN38=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"TYZPR06MB6745","Received-SPF":"pass client-ip=2a01:111:f403:c40f::6;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=SEYPR02CU001.outbound.protection.outlook.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"EHCI supports 64-bit addressing through the CTRLDSSEGMENT register,\nwhich provides the upper 32 bits of descriptor addresses when the\ncontroller advertises 64-bit capability.\n\nCurrently QEMU EHCI model only partially supports this functionality and\ndescriptor addresses are effectively treated as 32-bit. This becomes\nproblematic on systems where system memory is located above the 4GB\nboundary.\n\nThe Linux EHCI driver enables 64-bit addressing if the controller\nadvertises the capability. During initialization it programs the\nsegment register to zero:\n\n https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hcd.c#L600\n\nThe driver also notes that descriptor structures allocated from the\nDMA pool use segment zero semantics. Descriptor memory is allocated\nusing the DMA API and platforms may configure a 64-bit DMA mask,\nallowing descriptor memory to be placed above 4GB.\n\nOn AST2700 platforms, system DRAM is mapped at 0x400000000. As a\nresult, descriptor addresses constructed directly from the EHCI\nregisters do not match the actual system addresses used by the\ncontroller when accessing queue heads (QH) and queue element transfer\ndescriptors (qTD).\n\nThis patch series implements full 64-bit descriptor addressing support\nin the EHCI emulation. Descriptor address handling is updated to use\n64-bit values and the descriptor structures (QH, qTD, iTD and siTD)\nare extended to support the upper address bits provided by the segment\nregister.\n\nIn addition, a descriptor-addr-offset property is introduced so\nplatforms can apply an address translation when descriptor memory\nresides above the 4GB boundary.\n\nThe AST2700 machine uses this property to account for its DRAM mapping\nat 0x400000000 and enables 64-bit EHCI DMA addressing.\n\nTest Result:\n1. EHCI 32bits with ast2600-evb machine\nCommand line:\n./build/qemu-system-arm \\\n -machine ast2600-evb \\\n -m 1G \\\n -drive file=image-bmc,if=mtd,format=raw \\\n -nographic \\\n -device usb-kbd,bus=usb-bus.1,id=mykbd \\\n -drive id=usbdisk,if=none,file=image0.ext4,format=raw \\\n -device usb-storage,bus=usb-bus.1,id=mystorage,drive=usbdisk\n -snapshot \\\n -nographic\nResult:\nunable to initialize usb specBus 001 Device 001: ID 1d6b:0002 Linux 6.18.3-v00.08.01-g172b7e27a30d ehci_hcd EHCI Host Controller\nBus 001 Device 002: ID 0627:0001 QEMU QEMU USB Keyboard\nBus 001 Device 003: ID 46f4:0001 QEMU QEMU USB HARDDRIVE\nBus 002 Device 001: ID 1d6b:0001 Linux 6.18.3-v00.08.01-g172b7e27a30d uhci_hcd Generic UHCI Host Controller\n\n2. EHCI 64bits with ast2700a2-evb machine\nCommand line:\n./build/qemu-system-aarch64 -M ast2700a2-evb -nographic\\\n -bios ast27x0_bootrom.bin \\\n -drive file=image-bmc,format=raw,if=mtd \\\n -snapshot \\\n -device usb-kbd,bus=usb-bus.3,id=mykbd \\\n -drive id=usbdisk,if=none,file=image0.ext4,format=raw \\\n -device usb-storage,bus=usb-bus.3,id=mystorage,drive=usbdisk\nResult:\nroot@ast2700-default:~# lsusb\nunable to initialize usb specBus 001 Device 001: ID 1d6b:0001 Linux 6.18.3-v00.08.01-g172b7e27a30d uhci_hcd Generic UHCI Host Controller\nBus 002 Device 001: ID 1d6b:0002 Linux 6.18.3-v00.08.01-g172b7e27a30d ehci_hcd EHCI Host Controller\nBus 002 Device 002: ID 0627:0001 QEMU QEMU USB Keyboard\nBus 002 Device 003: ID 46f4:0001 QEMU QEMU USB HARDDRIVE\n \nv1\n 1. Fix checkpatch coding style issues\n 2. Implement 64-bit addressing for QH/qTD/iTD/siTD descriptors\n 3. Add descriptor address offset property\n 4. Enable 64-bit EHCI DMA addressing on AST2700\n 5. Configure descriptor address offset for AST2700\n\nv2\n 1. Remove unused EHCIfstn structure and dead code\n 2. Replace fprintf(stderr, ...) with qemu_log_mask(LOG_GUEST_ERROR)\n 3. Replace DPRINTF debug logs with trace events\n 4. Add functional tests for USB EHCI on AST2600 and AST2700 A1/A2\n 5. Fix review issue\n \nJamin Lin (17):\n hw/usb/hcd-ehci: Remove unused EHCIfstn structure and dead code\n hw/usb/hcd-ehci.h: Fix coding style issues reported by checkpatch\n hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch\n hw/usb/hcd-ehci.c: Replace fprintf(stderr, ...) with\n qemu_log_mask(LOG_GUEST_ERROR)\n hw/usb/hcd-ehci: Replace DPRINTF debug logs with trace events\n hw/usb/hcd-ehci: Change descriptor addresses to 64-bit\n hw/usb/hcd-ehci: Add property to advertise 64-bit addressing\n capability\n hw/usb/hcd-ehci: Reject CTRLDSSEGMENT writes without 64-bit capability\n hw/usb/hcd-ehci: Implement 64-bit QH descriptor addressing\n hw/usb/hcd-ehci: Implement 64-bit qTD descriptor addressing\n hw/usb/hcd-ehci: Implement 64-bit iTD descriptor addressing\n hw/usb/hcd-ehci: Implement 64-bit siTD descriptor addressing\n hw/usb/hcd-ehci: Add descriptor address offset property\n hw/arm/aspeed_ast27x0: Enable 64-bit EHCI DMA addressing\n hw/arm/aspeed_ast27x0: Set EHCI descriptor address offset\n tests/functional/arm/test_aspeed_ast2600_sdk: Add USB EHCI test for\n AST2600 SDK\n tests/functional/aarch64/test_aspeed_ast2700: Add USB EHCI test for\n AST2700 A1/A2\n\n hw/usb/hcd-ehci.h | 55 ++-\n hw/arm/aspeed_ast27x0.c | 5 +\n hw/usb/hcd-ehci-pci.c | 4 +\n hw/usb/hcd-ehci-sysbus.c | 4 +\n hw/usb/hcd-ehci.c | 371 ++++++++++--------\n hw/usb/trace-events | 25 +-\n .../aarch64/test_aspeed_ast2700a1.py | 7 +\n .../aarch64/test_aspeed_ast2700a2.py | 7 +\n .../functional/arm/test_aspeed_ast2600_sdk.py | 7 +\n 9 files changed, 294 insertions(+), 191 deletions(-)"}