{"id":2219410,"url":"http://patchwork.ozlabs.org/api/covers/2219410/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260402230626.3826719-1-grzegorz.nitka@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260402230626.3826719-1-grzegorz.nitka@intel.com>","list_archive_url":null,"date":"2026-04-02T23:06:18","name":"[v5,net-next,0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825","submitter":{"id":82711,"url":"http://patchwork.ozlabs.org/api/people/82711/?format=json","name":"Grzegorz Nitka","email":"grzegorz.nitka@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260402230626.3826719-1-grzegorz.nitka@intel.com/mbox/","series":[{"id":498564,"url":"http://patchwork.ozlabs.org/api/series/498564/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=498564","date":"2026-04-02T23:06:18","name":"dpll/ice: Add TXC DPLL type and full TX reference clock control for E825","version":5,"mbox":"http://patchwork.ozlabs.org/series/498564/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2219410/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=MjlhkGew;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.138; 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a=\"76123031\"","E=Sophos;i=\"6.23,156,1770624000\"; d=\"scan'208\";a=\"76123031\"","E=Sophos;i=\"6.23,156,1770624000\"; d=\"scan'208\";a=\"227044401\""],"X-ExtLoop1":"1","From":"Grzegorz Nitka ","To":"netdev@vger.kernel.org","Date":"Fri, 3 Apr 2026 01:06:18 +0200","Message-Id":"<20260402230626.3826719-1-grzegorz.nitka@intel.com>","X-Mailer":"git-send-email 2.39.3","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775171408; x=1806707408;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=ajZW05UQdtaVy0CBuJYX5951jU8a/swEG1qZqdkSpeY=;\n b=IZ7r6ee1CvvlxzWHRk+SikEQqStW1kPDKsv06jjb6M8GnXey3EGFNB96\n kPrlUTWZEOUkQ+D3m4p9q1sEE2chg5KLcSPvuPz8SUruujL8qeSVqMhuY\n 4ehItWS4GRX7bZ1uzTH1Xv6qIaPvkDc63QeE2QeUwgRXFnKZvfWohVhRg\n jZXAFRHiKNp+4h5A0swBb87IRAEQ8+zrNbi0lPthhhQ6IxKhlljpToSfY\n QLXbRkaWBCO7HJhKRqJ8+xElogX1pVHgYHCXbaRScyHptEBDvFqhTmR1l\n yPCRwgJi3hLRqS/awF4+C8i/jGeCKQV4fUq53I0t/Zg1KmWtdSr4cnOVH\n Q==;","X-Mailman-Original-Authentication-Results":["smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp3.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=IZ7r6ee1"],"Subject":"[Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC DPLL\n type and full TX reference clock control for E825","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"ivecera@redhat.com, vadim.fedorenko@linux.dev, kuba@kernel.org,\n jiri@resnulli.us, edumazet@google.com, przemyslaw.kitszel@intel.com,\n richardcochran@gmail.com, donald.hunter@gmail.com,\n linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com,\n andrew+netdev@lunn.ch, intel-wired-lan@lists.osuosl.org, horms@kernel.org,\n Prathosh.Satish@microchip.com, anthony.l.nguyen@intel.com, pabeni@redhat.com,\n davem@davemloft.net","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"NOTE: This series is intentionally submitted on net-next (not\nintel-wired-lan) as early feedback of DPLL subsystem changes is\nwelcomed. In the past possible approaches were discussed in [1].\n\nThis series adds TX reference clock support for E825 devices and exposes\nTX clock selection and synchronization status via the Linux DPLL\nsubsystem.\nE825 hardware contains a dedicated Tx clock (TXC) domain that is\ndistinct\nfrom PPS and EEC. TX reference clock selection is device‑wide, shared\nacross ports, and mediated by firmware as part of the link bring‑up\nprocess. As a result, TX clock selection intent may differ from the\neffective hardware configuration, and software must verify the outcome\nafter link‑up.\nTo support this, the series introduces TXC support incrementally across\nthe DPLL core and the ice driver:\n\n- add a new DPLL type (TXC) to represent transmit clock generators;\n- relax DPLL pin registration rules for firmware‑described shared pins\n and extend pin notifications with a source identifier;\n- allow dynamic state control of SyncE reference pins where hardware\n supports it;\n- add CPI infrastructure for PHY‑side TX clock control on E825C;\n- introduce a TXC DPLL device and TX reference clock pins (EXT_EREF0 and\n SYNCE) in the ice driver;\n- extend the Restart Auto‑Negotiation command to carry a TX reference\n clock index;\n- implement hardware‑backed TX reference clock switching, post‑link\n- verification, and TX synchronization reporting.\n\nTXCLK pins report TX reference topology only. Actual synchronization\nsuccess is reported via the TXC DPLL lock status, which is updated after\nhardware verification: external Tx references report LOCKED, while the\ninternal ENET/TXCO source reports UNLOCKED.\nThis provides reliable TX reference selection and observability on E825\ndevices using standard DPLL interfaces, without conflating user intent\nwith effective hardware behavior.\n\n[1] https://lore.kernel.org/netdev/20250905160333.715c34ac@kernel.org/\n\nChanges in v5:\n - rebased\n - reworded cover letter\n - replace 'ntfy_src' new argument name with 'src_clk_id' and use it\n consistently in DPLL notification calls (patch 3/8)\n - reworded commit message (patch 5/8)\n - use FIELD_PREP/GENMSK macros instead of struct bitfields (patch 6/8)\n - reworded commit message (patch 5/8, patch 8/8)\n - refactor the code to avoid sleeping while DPLL mutex is held (using\n work_queue, patch 8/8)\n - added TXCLK pins and TXC DPLL notifications (patch 8/8)\n - removed 'unused clock disable' mechanism from the scope of this series\n\nChanges in v4:\n - rebased\n - edited, shortened the commit message in 3/8 patch\n - moved ice_get_ctrl_pf to the header file (patch 8/8) and\n removed duplicated static definitions from ice_ptp and ice_txlck\n modules\n - add NULL/invalid pointer checker for returned pointer from\n ice_get_ctrl_pf (patch 8/8)\n - edited error message in case AN restart failure (patch 8/8)\n\nChanges in v3:\n- improved commit message (patch 1/8, AI review comment)\n- improved deinitialization path in ice_dpll_deinit_txclk_pins to\n avoid potential NULL dereference. NULL checking moved to\n ice_dpll_unregister_pins (patch 5/8, found by AI review)\n- removed redundant semicolon (patch 6/8)\n\nChanges in v2:\n- rebased\n- added autogenerated DPLL files (patch 1/8)\n- fixed checkpatch 'parenthesis alignment' warning (patch 2/8)\n- fixed error path in ice_dpll_init_txclk_pins (AI warning, patch 5/8)\n- fixed kdoc warnings (patch 6/8, patch 8/8)\n\nGrzegorz Nitka (8):\n dpll: add new DPLL type for transmit clock (TXC) usage\n dpll: allow registering FW-identified pin with a different DPLL\n dpll: extend pin notifier and netlink events with notification source\n ID\n dpll: zl3073x: allow SyncE_Ref pin state change\n ice: introduce TXC DPLL device and TX ref clock pin framework for E825\n ice: implement CPI support for E825C\n ice: add Tx reference clock index handling to AN restart command\n ice: implement E825 TX ref clock control and TXC hardware sync status\n\n Documentation/netlink/specs/dpll.yaml | 3 +\n drivers/dpll/dpll_core.c | 32 +-\n drivers/dpll/dpll_core.h | 3 +-\n drivers/dpll/dpll_netlink.c | 10 +-\n drivers/dpll/dpll_netlink.h | 4 +-\n drivers/dpll/dpll_nl.c | 2 +-\n drivers/dpll/zl3073x/prop.c | 9 +\n drivers/net/ethernet/intel/ice/Makefile | 2 +-\n drivers/net/ethernet/intel/ice/ice.h | 12 +\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 +\n drivers/net/ethernet/intel/ice/ice_common.c | 5 +-\n drivers/net/ethernet/intel/ice/ice_common.h | 2 +-\n drivers/net/ethernet/intel/ice/ice_cpi.c | 337 ++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_cpi.h | 61 +++\n drivers/net/ethernet/intel/ice/ice_dpll.c | 380 ++++++++++++++++--\n drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 3 +-\n drivers/net/ethernet/intel/ice/ice_ptp.c | 26 +-\n drivers/net/ethernet/intel/ice/ice_ptp.h | 7 +\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 37 ++\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 34 ++\n drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 5 +-\n drivers/net/ethernet/intel/ice/ice_txclk.c | 241 +++++++++++\n drivers/net/ethernet/intel/ice/ice_txclk.h | 38 ++\n include/linux/dpll.h | 1 +\n include/uapi/linux/dpll.h | 2 +\n 26 files changed, 1215 insertions(+), 53 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.h\n create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.h\n\n\nbase-commit: f35340f2d653f1003602878403c901396ab03c17"}