{"id":2215708,"url":"http://patchwork.ozlabs.org/api/covers/2215708/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1774421649.git.15fengyuan@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-03-25T07:09:04","name":"[v3,0/2] tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev","submitter":{"id":92576,"url":"http://patchwork.ozlabs.org/api/people/92576/?format=json","name":"Fengyuan Yu","email":"15fengyuan@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1774421649.git.15fengyuan@gmail.com/mbox/","series":[{"id":497387,"url":"http://patchwork.ozlabs.org/api/series/497387/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497387","date":"2026-03-25T07:09:04","name":"tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev","version":3,"mbox":"http://patchwork.ozlabs.org/series/497387/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2215708/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=GYY+yv2h;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\" , Jason Wang ,\n Yi Liu ,\n =?utf-8?q?Cl=C3=A9ment_Mathieu--Drif?= ,\n Fabiano Rosas , Laurent Vivier ,\n Paolo Bonzini , Tao Tang ","Cc":"qemu-devel@nongnu.org, Chao Liu ,\n Fengyuan Yu <15fengyuan@gmail.com>","Subject":"[PATCH v3 0/2] tests/qtest: Add Intel IOMMU bare-metal test using\n iommu-testdev","Date":"Wed, 25 Mar 2026 15:09:04 +0800","Message-Id":"","X-Mailer":"git-send-email 2.39.5","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1035;\n envelope-from=15fengyuan@gmail.com; helo=mail-pj1-x1035.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Hi,\n\nThis patch series adds a bare-metal qtest for the Intel IOMMU (VT-d) using\nthe iommu-testdev framework. The test exercises address translation paths\nwithout requiring a full guest OS boot.\n\nMotivation\n----------\n\nThe Intel IOMMU implementation in QEMU supports various translation \nmodes. Currently, comprehensive testing of these translation paths \nrequires booting a full guest OS with appropriate drivers, which is \ntime-consuming and makes regression testing difficult.\n\nThis new test fills that gap by using iommu-testdev to trigger DMA\ntransactions and validate the IOMMU's translation logic directly.\n\nTest Coverage\n-------------\n\nThe new test provides:\n- Legacy pass-through mode (identity mapping)\n- Legacy translated mode with 4-level second-level page table walks\n- Scalable pass-through mode (PGTT=100b)\n- Scalable second-level translation mode (PGTT=010b)\n- Scalable first-level translation mode (PGTT=001b)\n- Root/Context Entry, PASID Directory/Table Entry configuration\n- Complete 48-bit address space translation\n- End-to-end DMA verification with memory validation\n\nTesting\n-------\n\nQTEST_QEMU_BINARY=./build/qemu-system-x86_64 \\\n ./build/tests/qtest/iommu-intel-test --tap -k\n\nChanges v1 -> v2\n----------------\n- Rebase onto latest upstream to resolve compilation errors\n- Add scalable translation mode tests (SLT, FLT, PassThrough)\n- Add spec-aligned register field comments for improved readability\n\nChanges v2 -> v3\n----------------\n- Fix MAINTAINERS: move qos-intel-iommu* to \"QTest IOMMU helpers\" \n section, move iommu-intel-test.c entry to patch 2/2, remove\n duplicate entries from x86 general section\n- Remove duplicate Q35_IOMMU_BASE macro, use existing\n Q35_HOST_BRIDGE_IOMMU_ADDR instead\n- Drop unused QVTD_TM_SCALABLE_NESTED enum value\n- Fix parameter alignment in function declarations\n- Clarify qvtd_build_dma_attrs() comment: PASID=0 is reached via\n VT-d's no-PASID fallback, not via DMA attributes\n\nThanks,\nFengyuan\n\nFengyuan Yu (2):\n tests/qtest/libqos: Add Intel IOMMU helper library\n tests/qtest: Add Intel IOMMU bare-metal test\n\n MAINTAINERS | 2 +\n tests/qtest/iommu-intel-test.c | 216 +++++++++++++\n tests/qtest/libqos/meson.build | 3 +\n tests/qtest/libqos/qos-intel-iommu.c | 454 +++++++++++++++++++++++++++\n tests/qtest/libqos/qos-intel-iommu.h | 185 +++++++++++\n tests/qtest/meson.build | 2 +\n 6 files changed, 862 insertions(+)\n create mode 100644 tests/qtest/iommu-intel-test.c\n create mode 100644 tests/qtest/libqos/qos-intel-iommu.c\n create mode 100644 tests/qtest/libqos/qos-intel-iommu.h"}