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helo=mail-pj1-x1029.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This series contains two fixes for the RISC-V IOMMU implementation:\n\n1. Fix a bug in the HPM (Hardware Performance Monitor) timer setup where\n irq_overflow_left was not properly reset, causing stale values from\n previous timer setups to affect new timer behavior.\n\n2. Add proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP\n (Performance Monitor Interrupt Pending) bit, which was missing from\n the IPSR register implementation.\n\n---\nChange in V2\n Add commit message\n\nJay Chang (2):\n hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug\n hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support\n\n hw/riscv/riscv-iommu-bits.h | 1 +\n hw/riscv/riscv-iommu-hpm.c | 1 +\n hw/riscv/riscv-iommu.c | 4 ++++\n 3 files changed, 6 insertions(+)"}