{"id":2070369,"url":"http://patchwork.ozlabs.org/api/covers/2070369/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20250409023711.2960618-1-maobibo@loongson.cn/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20250409023711.2960618-1-maobibo@loongson.cn>","list_archive_url":null,"date":"2025-04-09T02:36:55","name":"[v3,00/16] hw/intc/loongarch_pch: Cleanup with memory region ops","submitter":{"id":78914,"url":"http://patchwork.ozlabs.org/api/people/78914/?format=json","name":"Bibo Mao","email":"maobibo@loongson.cn"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20250409023711.2960618-1-maobibo@loongson.cn/mbox/","series":[{"id":451861,"url":"http://patchwork.ozlabs.org/api/series/451861/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=451861","date":"2025-04-09T02:37:00","name":"hw/intc/loongarch_pch: Cleanup with memory region ops","version":3,"mbox":"http://patchwork.ozlabs.org/series/451861/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2070369/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ZXRwn0LHgz1yHS\n\tfor ; Wed, 9 Apr 2025 12:39:21 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1u2LJi-0006Vi-Vl; Tue, 08 Apr 2025 22:37:31 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1u2LJh-0006UO-4W\n for qemu-devel@nongnu.org; Tue, 08 Apr 2025 22:37:29 -0400","from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1u2LJc-0007nA-UI\n for qemu-devel@nongnu.org; Tue, 08 Apr 2025 22:37:28 -0400","from loongson.cn (unknown [10.2.10.34])\n by gateway (Coremail) with SMTP id _____8CxyuBY3fVnDK+1AA--.40299S3;\n Wed, 09 Apr 2025 10:37:12 +0800 (CST)","from localhost.localdomain (unknown [10.2.10.34])\n by front1 (Coremail) with SMTP id qMiowMBxLsdY3fVnnsR1AA--.28294S2;\n Wed, 09 Apr 2025 10:37:12 +0800 (CST)"],"From":"Bibo Mao ","To":"Song Gao ","Cc":"Jiaxun Yang ,\n\tqemu-devel@nongnu.org","Subject":"[PATCH v3 00/16] hw/intc/loongarch_pch: Cleanup with memory region\n ops","Date":"Wed, 9 Apr 2025 10:36:55 +0800","Message-Id":"<20250409023711.2960618-1-maobibo@loongson.cn>","X-Mailer":"git-send-email 2.39.3","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"qMiowMBxLsdY3fVnnsR1AA--.28294S2","X-CM-SenderInfo":"xpdruxter6z05rqj20fqof0/","X-Coremail-Antispam":"1Uk129KBj93XoWxCw47Cw47Cw45ZF48JFyfKrX_yoW5Gry5p3\n 93uw1Ykrn7JrsrXFWkZa4rWFZ093Z3u3429FsIyrWIkr13CF1UZrW8Z34jqFyUG34xJryq\n qa18G347XF4UAwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUyEb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_\n GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4\n xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v2\n 6r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwI\n xGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480\n Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7\n IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k2\n 6cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxV\n AFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8czVUUUUUU==","Received-SPF":"pass client-ip=114.242.206.163;\n envelope-from=maobibo@loongson.cn;\n helo=mail.loongson.cn","X-Spam_score_int":"-18","X-Spam_score":"-1.9","X-Spam_bar":"-","X-Spam_report":"(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This series patchset is to clean up with memory regions of loongarch pch\npic interrupt controller. Originally there are three iomem regions:\niomem32_low, iomem8, iomem32_highm. Since these regions only support\n4 bytes/1 byte/4 bytes access, it is divided into three regions.\n\nNow it is merged into one region, this regions supports 1/2/4/8 bytes\naccess.\n\nPatch 1-6 is to replace register name, no function change.\nPatch 7-16 is to use unifed memory region iomem, and supports 1/2/4/8\nbytes access with read/write ops for this region, and merge three\nregions above into one.\n\n---\n v2 ... v3:\n 1. Set address aligned with 8 bytes in memory region function\n pch_pic_read() and pch_pic_write(), and only compare register\n base address with 8 bytes aligned one.\n 2. Replace 0xff/0xffff with UCHAR_MAX/USHRT_MAX.\n\n v1 ... v2:\n 1. Add 1/2/4/8 bytes access support with memory region read and\n write ops.\n 2. Merge three memory regions iomem32_low, iomem8 and iomem32_high\n into one region iomem.\n 3. Merge trace functions for ops in above three memory regions into\n one trace function\n---\n\nBibo Mao (16):\n hw/intc/loongarch_pch: Modify name of some registers\n hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET with\n PCH_PIC_xxx\n hw/intc/loongarch_pch: Remove some duplicate macro\n hw/intc/loongarch_pch: Set version information at initial stage\n hw/intc/loongarch_pch: Use relative address in MemoryRegionOps\n hw/intc/loongarch_pch: Discard write operation with ISR register\n hw/intc/loongarch_pch: Use generic read callback for iomem32_low\n region\n hw/intc/loongarch_pch: Use generic read callback for iomem32_high\n region\n hw/intc/loongarch_pch: Use generic read callback for iomem8 region\n hw/intc/loongarch_pch: Use generic write callback for iomem32_low\n region\n hw/intc/loongarch_pch: Use generic write callback for iomem32_high\n region\n hw/intc/loongarch_pch: Use generic write callback for iomem8 region\n hw/intc/loongarch_pch: Use unified trace event for memory region ops\n hw/intc/loongarch_pch: Rename memory region iomem32_low with iomem\n hw/intc/loongarch_pch: Set flexible memory access size with iomem\n region\n hw/intc/loongarch_pch: Merge three memory region into one\n\n hw/intc/loongarch_pch_pic.c | 344 +++++++++----------------\n hw/intc/trace-events | 8 +-\n hw/loongarch/virt.c | 6 -\n include/hw/intc/loongarch_pic_common.h | 57 ++--\n 4 files changed, 152 insertions(+), 263 deletions(-)\n\n\nbase-commit: dfaecc04c46d298e9ee81bd0ca96d8754f1c27ed"}