{"id":1839931,"url":"http://patchwork.ozlabs.org/api/covers/1839931/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20230926194951.183767-1-dbarboza@ventanamicro.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230926194951.183767-1-dbarboza@ventanamicro.com>","list_archive_url":null,"date":"2023-09-26T19:49:44","name":"[0/6] riscv: RVA22U64 profile support","submitter":{"id":85468,"url":"http://patchwork.ozlabs.org/api/people/85468/?format=json","name":"Daniel Henrique Barboza","email":"dbarboza@ventanamicro.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20230926194951.183767-1-dbarboza@ventanamicro.com/mbox/","series":[{"id":374996,"url":"http://patchwork.ozlabs.org/api/series/374996/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=374996","date":"2023-09-26T19:49:50","name":"riscv: RVA22U64 profile support","version":1,"mbox":"http://patchwork.ozlabs.org/series/374996/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/1839931/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com\n header.a=rsa-sha256 header.s=google header.b=lULAwm91;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9P11XQ5z1ypM\n\tfor ; Wed, 27 Sep 2023 05:51:49 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1qlE4m-0003vZ-Q0; Tue, 26 Sep 2023 15:50:32 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1qlE4W-0003sX-0q\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:17 -0400","from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1qlE4G-0001IC-E6\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:15 -0400","by mail-pf1-x436.google.com with SMTP id\n d2e1a72fcca58-69101022969so8556821b3a.3\n for ; Tue, 26 Sep 2023 12:49:59 -0700 (PDT)","from grind.. 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Optional extensions were left behind\nand must be enabled by hand if desired. Since this is the first profile\nwe're adding, we'll need to add the base framework as well. \n\nThe RVA22U64 profile was chosen because qemu-riscv implements all its\nextensions, both mandatory and optional. That includes 'zicntr' and\n'zihpm', which we support for awhile but aren't adverting to userspace.\n\nOther design decisions made:\n\n- disabling a profile flag does nothing, i.e. we won't mass disable\n mandatory extensions of the rva22U64 profile if the user sets\n rva22u64=false;\n\n- profile support for vendor CPUs consists into checking if the CPU\n happens to have the mandatory extensions required for it. In case it\n doesn't we'll error out. This is done to follow the same prerogative\n we always had of not allowing extensions being enabled for vendor\n CPUs;\n\n- the KVM driver doesn't support profiles. In theory we could apply the\n same logic as for the vendor CPUs, but KVM has a long way to go before\n that becomes a factor. We'll revisit this decision when KVM is able to\n support at least one profile.\n\nPatch 5 (\"enable profile support for vendor CPUs\") needs the following\nseries to be applied beforehand:\n\n\"[PATCH 0/2] riscv: add extension properties for all cpus\"\n\nOtherwise we won't be able to add the profile flag to vendor CPUs.\n\n[1] https://lore.kernel.org/qemu-riscv/35a847a1-2720-14ab-61b0-c72d77d5f43b@ventanamicro.com/\n\nDaniel Henrique Barboza (6):\n target/riscv/cpu.c: add zicntr extension flag\n target/riscv/cpu.c: add zihpm extension flag\n target/riscv: add rva22u64 profile definition\n target/riscv/tcg: implement rva22u64 profile\n target/riscv/tcg-cpu.c: enable profile support for vendor CPUs\n target/riscv/kvm: add 'rva22u64' flag as unavailable\n\n target/riscv/cpu.c | 25 ++++++++++\n target/riscv/cpu.h | 10 ++++\n target/riscv/cpu_cfg.h | 2 +\n target/riscv/kvm/kvm-cpu.c | 5 +-\n target/riscv/tcg/tcg-cpu.c | 98 ++++++++++++++++++++++++++++++++++++++\n 5 files changed, 139 insertions(+), 1 deletion(-)"}