{"id":502922,"url":"http://patchwork.ozlabs.org/api/1.2/series/502922/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=502922","project":{"id":69,"url":"http://patchwork.ozlabs.org/api/1.2/projects/69/?format=json","name":"QEMU powerpc development","link_name":"qemu-ppc","list_id":"qemu-ppc.nongnu.org","list_email":"qemu-ppc@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Defer the IOMMU translation in the CPU path and support access_type","date":"2026-05-06T03:36:37","submitter":{"id":83153,"url":"http://patchwork.ozlabs.org/api/1.2/people/83153/?format=json","name":"Jim Shu","email":"jim.shu@sifive.com"},"version":3,"total":5,"received_total":5,"received_all":true,"mbox":"http://patchwork.ozlabs.org/series/502922/mbox/","cover_letter":{"id":2233280,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2233280/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/cover/20260506033642.3641390-1-jim.shu@sifive.com/","msgid":"<20260506033642.3641390-1-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:37","name":"[v3,0/5] Defer the IOMMU translation in the CPU path and support access_type","mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/cover/20260506033642.3641390-1-jim.shu@sifive.com/mbox/"},"patches":[{"id":2233290,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233290/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-2-jim.shu@sifive.com/","msgid":"<20260506033642.3641390-2-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:38","name":"[v3,1/5] accel/tcg: Pass access_type as an argument of tlb_set_page*()","mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-2-jim.shu@sifive.com/mbox/"},{"id":2233289,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233289/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-3-jim.shu@sifive.com/","msgid":"<20260506033642.3641390-3-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:39","name":"[v3,2/5] accel/tcg: address_space_translate*() will pass the correct iommu_flags","mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-3-jim.shu@sifive.com/mbox/"},{"id":2233283,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233283/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-4-jim.shu@sifive.com/","msgid":"<20260506033642.3641390-4-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:40","name":"[v3,3/5] accel/tcg: Provide early AS translate function","mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-4-jim.shu@sifive.com/mbox/"},{"id":2233286,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233286/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-5-jim.shu@sifive.com/","msgid":"<20260506033642.3641390-5-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:41","name":"[v3,4/5] accel/tcg: Add IOMMU lazy translation function","mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-5-jim.shu@sifive.com/mbox/"},{"id":2233291,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233291/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-6-jim.shu@sifive.com/","msgid":"<20260506033642.3641390-6-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:42","name":"[v3,5/5] accel/tcg: Support IOMMU lazy translation in CPU TLB","mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260506033642.3641390-6-jim.shu@sifive.com/mbox/"}]}