{"id":502465,"url":"http://patchwork.ozlabs.org/api/1.2/series/502465/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Remove SMMUv3 struct arm_smmu_cmdq_ent","date":"2026-05-01T14:29:09","submitter":{"id":79424,"url":"http://patchwork.ozlabs.org/api/1.2/people/79424/?format=json","name":"Jason Gunthorpe","email":"jgg@nvidia.com"},"version":1,"total":9,"received_total":9,"received_all":true,"mbox":"http://patchwork.ozlabs.org/series/502465/mbox/","cover_letter":{"id":2231887,"url":"http://patchwork.ozlabs.org/api/1.2/covers/2231887/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/cover/0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:09","name":"[0/9] Remove SMMUv3 struct arm_smmu_cmdq_ent","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/cover/0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},"patches":[{"id":2231891,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231891/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:10","name":"[1/9] iommu/arm-smmu-v3: Add struct arm_smmu_cmd to represent the HW format command","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/1-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231886,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231886/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:11","name":"[2/9] iommu/arm-smmu-v3: Use the HW arm_smmu_cmd in cmdq selection functions","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/2-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231892,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231892/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:12","name":"[3/9] iommu/arm-smmu-v3: Use the HW arm_smmu_cmd in cmdq submission functions","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/3-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231890,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231890/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:13","name":"[4/9] iommu/arm-smmu-v3: Convert arm_smmu_cmdq_batch cmds to struct arm_smmu_cmd","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231888,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231888/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/5-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<5-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:14","name":"[5/9] iommu/arm-smmu-v3: Remove CMDQ_OP_CFGI_CD_ALL from arm_smmu_cmdq_build_cmd()","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/5-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231894,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231894/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:15","name":"[6/9] iommu/arm-smmu-v3: Directly encode simple commands","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231895,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231895/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:16","name":"[7/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_ATC_INV","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231893,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231893/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:17","name":"[8/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_SYNC","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"},{"id":2231889,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231889/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","msgid":"<9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:18","name":"[9/9] iommu/arm-smmu-v3: Directly encode TLBI commands","mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/"}]}