{"id":949183,"url":"http://patchwork.ozlabs.org/api/1.2/patches/949183/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20180725133152.30898-4-miquel.raynal@bootlin.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/1.2/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20180725133152.30898-4-miquel.raynal@bootlin.com>","list_archive_url":null,"date":"2018-07-25T13:31:38","name":"[v5,03/17] mtd: rawnand: lpc32xx_mlc: convert driver to nand_scan()","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"41f0e5956f30582e5ffffdd97b12bca35db51f0e","submitter":{"id":73368,"url":"http://patchwork.ozlabs.org/api/1.2/people/73368/?format=json","name":"Miquel Raynal","email":"miquel.raynal@bootlin.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20180725133152.30898-4-miquel.raynal@bootlin.com/mbox/","series":[{"id":57526,"url":"http://patchwork.ozlabs.org/api/1.2/series/57526/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=57526","date":"2018-07-25T13:31:36","name":"Allow dynamic allocations during NAND chip identification phase","version":5,"mbox":"http://patchwork.ozlabs.org/series/57526/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/949183/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/949183/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Two helpers have been added to the core to do all kind of controller\nside configuration/initialization between the detection phase and the\nfinal NAND scan. Implement these hooks so that we can convert the driver\nto just use nand_scan() instead of the nand_scan_ident() +\nnand_scan_tail() pair.\n\nSigned-off-by: Miquel Raynal \n---\n drivers/mtd/nand/raw/lpc32xx_mlc.c | 61 +++++++++++++++++++++-----------------\n 1 file changed, 33 insertions(+), 28 deletions(-)","diff":"diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c\nindex 052d123a8304..e82abada130a 100644\n--- a/drivers/mtd/nand/raw/lpc32xx_mlc.c\n+++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c\n@@ -184,6 +184,7 @@ static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {\n };\n \n struct lpc32xx_nand_host {\n+\tstruct platform_device\t*pdev;\n \tstruct nand_chip\tnand_chip;\n \tstruct lpc32xx_mlc_platform_data *pdata;\n \tstruct clk\t\t*clk;\n@@ -653,6 +654,32 @@ static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)\n \treturn ncfg;\n }\n \n+static int lpc32xx_nand_attach_chip(struct nand_chip *chip)\n+{\n+\tstruct mtd_info *mtd = nand_to_mtd(chip);\n+\tstruct lpc32xx_nand_host *host = nand_get_controller_data(chip);\n+\tstruct device *dev = &host->pdev->dev;\n+\n+\thost->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);\n+\tif (!host->dma_buf)\n+\t\treturn -ENOMEM;\n+\n+\thost->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);\n+\tif (!host->dummy_buf)\n+\t\treturn -ENOMEM;\n+\n+\tchip->ecc.mode = NAND_ECC_HW;\n+\tchip->ecc.size = 512;\n+\tmtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);\n+\thost->mlcsubpages = mtd->writesize / 512;\n+\n+\treturn 0;\n+}\n+\n+static const struct nand_controller_ops lpc32xx_nand_controller_ops = {\n+\t.attach_chip = lpc32xx_nand_attach_chip,\n+};\n+\n /*\n * Probe for NAND controller\n */\n@@ -669,6 +696,8 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)\n \tif (!host)\n \t\treturn -ENOMEM;\n \n+\thost->pdev = pdev;\n+\n \trc = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n \thost->io_base = devm_ioremap_resource(&pdev->dev, rc);\n \tif (IS_ERR(host->io_base))\n@@ -748,31 +777,6 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)\n \t\t}\n \t}\n \n-\t/*\n-\t * Scan to find existance of the device and\n-\t * Get the type of NAND device SMALL block or LARGE block\n-\t */\n-\tres = nand_scan_ident(mtd, 1, NULL);\n-\tif (res)\n-\t\tgoto release_dma_chan;\n-\n-\thost->dma_buf = devm_kzalloc(&pdev->dev, mtd->writesize, GFP_KERNEL);\n-\tif (!host->dma_buf) {\n-\t\tres = -ENOMEM;\n-\t\tgoto release_dma_chan;\n-\t}\n-\n-\thost->dummy_buf = devm_kzalloc(&pdev->dev, mtd->writesize, GFP_KERNEL);\n-\tif (!host->dummy_buf) {\n-\t\tres = -ENOMEM;\n-\t\tgoto release_dma_chan;\n-\t}\n-\n-\tnand_chip->ecc.mode = NAND_ECC_HW;\n-\tnand_chip->ecc.size = 512;\n-\tmtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);\n-\thost->mlcsubpages = mtd->writesize / 512;\n-\n \t/* initially clear interrupt status */\n \treadb(MLC_IRQ_SR(host->io_base));\n \n@@ -794,10 +798,11 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)\n \t}\n \n \t/*\n-\t * Fills out all the uninitialized function pointers with the defaults\n-\t * And scans for a bad block table if appropriate.\n+\t * Scan to find existence of the device and get the type of NAND device:\n+\t * SMALL block or LARGE block.\n \t */\n-\tres = nand_scan_tail(mtd);\n+\tnand_chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;\n+\tres = nand_scan(mtd, 1);\n \tif (res)\n \t\tgoto free_irq;\n \n","prefixes":["v5","03/17"]}