{"id":949181,"url":"http://patchwork.ozlabs.org/api/1.2/patches/949181/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20180725133152.30898-2-miquel.raynal@bootlin.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/1.2/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20180725133152.30898-2-miquel.raynal@bootlin.com>","list_archive_url":null,"date":"2018-07-25T13:31:36","name":"[v5,01/17] mtd: rawnand: brcmnand: convert driver to nand_scan()","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"b09492b9cbe209f1a51fc7c5d466dad0dc3e713a","submitter":{"id":73368,"url":"http://patchwork.ozlabs.org/api/1.2/people/73368/?format=json","name":"Miquel Raynal","email":"miquel.raynal@bootlin.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20180725133152.30898-2-miquel.raynal@bootlin.com/mbox/","series":[{"id":57526,"url":"http://patchwork.ozlabs.org/api/1.2/series/57526/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=57526","date":"2018-07-25T13:31:36","name":"Allow dynamic allocations during NAND chip identification phase","version":5,"mbox":"http://patchwork.ozlabs.org/series/57526/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/949181/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/949181/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Two helpers have been added to the core to do all kind of controller\nside configuration/initialization between the detection phase and the\nfinal NAND scan. Implement these hooks so that we can convert the driver\nto just use nand_scan() instead of the nand_scan_ident() +\nnand_scan_tail() pair.\n\nSigned-off-by: Miquel Raynal \n---\n drivers/mtd/nand/raw/brcmnand/brcmnand.c | 63 ++++++++++++++++++--------------\n 1 file changed, 36 insertions(+), 27 deletions(-)","diff":"diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c\nindex 2e5efa0f9ea2..4b90d5b380c2 100644\n--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c\n+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c\n@@ -2208,6 +2208,40 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)\n \treturn 0;\n }\n \n+static int brcmnand_attach_chip(struct nand_chip *chip)\n+{\n+\tstruct mtd_info *mtd = nand_to_mtd(chip);\n+\tstruct brcmnand_host *host = nand_get_controller_data(chip);\n+\tint ret;\n+\n+\tchip->options |= NAND_NO_SUBPAGE_WRITE;\n+\t/*\n+\t * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA\n+\t * to/from, and have nand_base pass us a bounce buffer instead, as\n+\t * needed.\n+\t */\n+\tchip->options |= NAND_USE_BOUNCE_BUFFER;\n+\n+\tif (chip->bbt_options & NAND_BBT_USE_FLASH)\n+\t\tchip->bbt_options |= NAND_BBT_NO_OOB;\n+\n+\tif (brcmnand_setup_dev(host))\n+\t\treturn -ENXIO;\n+\n+\tchip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;\n+\n+\t/* only use our internal HW threshold */\n+\tmtd->bitflip_threshold = 1;\n+\n+\tret = brcmstb_choose_ecc_layout(host);\n+\n+\treturn ret;\n+}\n+\n+static const struct nand_controller_ops brcmnand_controller_ops = {\n+\t.attach_chip = brcmnand_attach_chip,\n+};\n+\n static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)\n {\n \tstruct brcmnand_controller *ctrl = host->ctrl;\n@@ -2267,33 +2301,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)\n \tnand_writereg(ctrl, cfg_offs,\n \t\t nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);\n \n-\tret = nand_scan_ident(mtd, 1, NULL);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tchip->options |= NAND_NO_SUBPAGE_WRITE;\n-\t/*\n-\t * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA\n-\t * to/from, and have nand_base pass us a bounce buffer instead, as\n-\t * needed.\n-\t */\n-\tchip->options |= NAND_USE_BOUNCE_BUFFER;\n-\n-\tif (chip->bbt_options & NAND_BBT_USE_FLASH)\n-\t\tchip->bbt_options |= NAND_BBT_NO_OOB;\n-\n-\tif (brcmnand_setup_dev(host))\n-\t\treturn -ENXIO;\n-\n-\tchip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;\n-\t/* only use our internal HW threshold */\n-\tmtd->bitflip_threshold = 1;\n-\n-\tret = brcmstb_choose_ecc_layout(host);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = nand_scan_tail(mtd);\n+\tret = nand_scan(mtd, 1);\n \tif (ret)\n \t\treturn ret;\n \n@@ -2434,6 +2442,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)\n \tinit_completion(&ctrl->done);\n \tinit_completion(&ctrl->dma_done);\n \tnand_controller_init(&ctrl->controller);\n+\tctrl->controller.ops = &brcmnand_controller_ops;\n \tINIT_LIST_HEAD(&ctrl->host_list);\n \n \t/* NAND register range */\n","prefixes":["v5","01/17"]}