{"id":834178,"url":"http://patchwork.ozlabs.org/api/1.2/patches/834178/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20171104085030.25430-13-saeedm@mellanox.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/1.2/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171104085030.25430-13-saeedm@mellanox.com>","list_archive_url":null,"date":"2017-11-04T08:50:30","name":"[net-next,12/12] net/mlx5e: Enable CQE based moderation on TX CQ","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"c1cc839d045f9c0d73bd832e39016f199ddd12cc","submitter":{"id":65299,"url":"http://patchwork.ozlabs.org/api/1.2/people/65299/?format=json","name":"Saeed Mahameed","email":"saeedm@mellanox.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/1.2/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20171104085030.25430-13-saeedm@mellanox.com/mbox/","series":[{"id":11869,"url":"http://patchwork.ozlabs.org/api/1.2/series/11869/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=11869","date":"2017-11-04T08:50:18","name":"[net-next,01/12] net/dcb: Add dscp to priority selector type","version":1,"mbox":"http://patchwork.ozlabs.org/series/11869/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/834178/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/834178/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yTXdT6vlqz9sBW\n\tfor ;\n\tSat, 4 Nov 2017 19:52:29 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932453AbdKDIwX (ORCPT );\n\tSat, 4 Nov 2017 04:52:23 -0400","from mail-il-dmz.mellanox.com ([193.47.165.129]:54616 \"EHLO\n\tmellanox.co.il\" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org\n\twith ESMTP id S932287AbdKDIwP (ORCPT\n\t); Sat, 4 Nov 2017 04:52:15 -0400","from Internal Mail-Server by MTLPINE1 (envelope-from\n\tsaeedm@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 4 Nov 2017 10:52:10 +0200","from mti-swat15.mti.labs.mlnx. (mti-swat15.mti.labs.mlnx\n\t[10.20.1.123])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id vA48pkia022678;\n\tSat, 4 Nov 2017 10:52:09 +0200"],"From":"Saeed Mahameed ","To":"\"David S. Miller\" ","Cc":"netdev@vger.kernel.org, Tal Gilboa ,\n\tSaeed Mahameed ","Subject":"[net-next 12/12] net/mlx5e: Enable CQE based moderation on TX CQ","Date":"Sat, 4 Nov 2017 01:50:30 -0700","Message-Id":"<20171104085030.25430-13-saeedm@mellanox.com>","X-Mailer":"git-send-email 2.14.2","In-Reply-To":"<20171104085030.25430-1-saeedm@mellanox.com>","References":"<20171104085030.25430-1-saeedm@mellanox.com>","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"From: Tal Gilboa \n\nBy using CQE based moderation on TX CQ we can reduce the number of TX\ninterrupt rate. Besides the benefit of less interrupts, this also\nallows the kernel to better utilize TSO. Since TSO has some CPU overhead,\nit might not aggregate when CPU is under high stress. By reducing the\ninterrupt rate and the CPU utilization, we can get better aggregation\nand better overall throughput.\nThe feature is enabled by default and has a private flag in ethtool\nfor control.\n\nThroughput, interrupt rate and TSO utilization improvements:\n(ConnectX-4Lx 40GbE, unidirectional, 1/16 TCP streams, 64B packets)\n---------------------------------------------------------\nMetric | Streams | CQE Based | EQE Based | improvement\n---------------------------------------------------------\nBW | 1 | 2.4Gb/s | 2.15Gb/s | +11.6%\nIR | 1 | 27Kips | 50.6Kips | -46.7%\nTSO Util | 1 | 74.6% | 71% | +5%\nBW | 16 | 29Gb/s | 25.85Gb/s | +12.2%\nIR | 16 | 482Kips | 745Kips | -35.3%\nTSO Util | 16 | 69.1% | 49% | +41.1%\n\n*BW = Bandwidth, IR = Interrupt rate, ips = interrupt per second.\nTSO Util = bytes in TSO sessions / all bytes transferred\n\nSigned-off-by: Tal Gilboa \nSigned-off-by: Saeed Mahameed \n\nSigned-off-by: Saeed Mahameed \n---\n drivers/net/ethernet/mellanox/mlx5/core/en.h | 9 +++--\n .../net/ethernet/mellanox/mlx5/core/en_ethtool.c | 39 +++++++++++++++++-----\n drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 38 +++++++++++++++------\n drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c | 8 +++--\n 4 files changed, 71 insertions(+), 23 deletions(-)","diff":"diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h\nindex 95facdf62c77..751f62cae969 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h\n@@ -106,6 +106,7 @@\n #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3\n #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20\n #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10\n+#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10\n #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20\n #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80\n #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2\n@@ -198,12 +199,14 @@ extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];\n \n static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {\n \t\"rx_cqe_moder\",\n+\t\"tx_cqe_moder\",\n \t\"rx_cqe_compress\",\n };\n \n enum mlx5e_priv_flag {\n \tMLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),\n-\tMLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),\n+\tMLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),\n+\tMLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),\n };\n \n #define MLX5E_SET_PFLAG(params, pflag, enable)\t\t\t\\\n@@ -223,6 +226,7 @@ enum mlx5e_priv_flag {\n struct mlx5e_cq_moder {\n \tu16 usec;\n \tu16 pkts;\n+\tu8 cq_period_mode;\n };\n \n struct mlx5e_params {\n@@ -234,7 +238,6 @@ struct mlx5e_params {\n \tu8 log_rq_size;\n \tu16 num_channels;\n \tu8 num_tc;\n-\tu8 rx_cq_period_mode;\n \tbool rx_cqe_compress_def;\n \tstruct mlx5e_cq_moder rx_cq_moderation;\n \tstruct mlx5e_cq_moder tx_cq_moderation;\n@@ -926,6 +929,8 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,\n \t\t\t\t int num_channels);\n int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);\n \n+void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,\n+\t\t\t\t u8 cq_period_mode);\n void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,\n \t\t\t\t u8 cq_period_mode);\n void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c\nindex 63d1ac695a75..23425f028405 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c\n@@ -1454,29 +1454,36 @@ static int mlx5e_get_module_eeprom(struct net_device *netdev,\n \n typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);\n \n-static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)\n+static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,\n+\t\t\t\t bool is_rx_cq)\n {\n \tstruct mlx5e_priv *priv = netdev_priv(netdev);\n \tstruct mlx5_core_dev *mdev = priv->mdev;\n \tstruct mlx5e_channels new_channels = {};\n-\tbool rx_mode_changed;\n-\tu8 rx_cq_period_mode;\n+\tbool mode_changed;\n+\tu8 cq_period_mode, current_cq_period_mode;\n \tint err = 0;\n \n-\trx_cq_period_mode = enable ?\n+\tcq_period_mode = enable ?\n \t\tMLX5_CQ_PERIOD_MODE_START_FROM_CQE :\n \t\tMLX5_CQ_PERIOD_MODE_START_FROM_EQE;\n-\trx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;\n+\tcurrent_cq_period_mode = is_rx_cq ?\n+\t\tpriv->channels.params.rx_cq_moderation.cq_period_mode :\n+\t\tpriv->channels.params.tx_cq_moderation.cq_period_mode;\n+\tmode_changed = cq_period_mode != current_cq_period_mode;\n \n-\tif (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&\n+\tif (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&\n \t !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))\n \t\treturn -EOPNOTSUPP;\n \n-\tif (!rx_mode_changed)\n+\tif (!mode_changed)\n \t\treturn 0;\n \n \tnew_channels.params = priv->channels.params;\n-\tmlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);\n+\tif (is_rx_cq)\n+\t\tmlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);\n+\telse\n+\t\tmlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);\n \n \tif (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {\n \t\tpriv->channels.params = new_channels.params;\n@@ -1491,6 +1498,16 @@ static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)\n \treturn 0;\n }\n \n+static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)\n+{\n+\treturn set_pflag_cqe_based_moder(netdev, enable, false);\n+}\n+\n+static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)\n+{\n+\treturn set_pflag_cqe_based_moder(netdev, enable, true);\n+}\n+\n int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)\n {\n \tbool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);\n@@ -1578,6 +1595,12 @@ static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)\n \tif (err)\n \t\tgoto out;\n \n+\terr = mlx5e_handle_pflag(netdev, pflags,\n+\t\t\t\t MLX5E_PFLAG_TX_CQE_BASED_MODER,\n+\t\t\t\t set_pflag_tx_cqe_based_moder);\n+\tif (err)\n+\t\tgoto out;\n+\n \terr = mlx5e_handle_pflag(netdev, pflags,\n \t\t\t\t MLX5E_PFLAG_RX_CQE_COMPRESS,\n \t\t\t\t set_pflag_rx_cqe_compress);\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\nindex 73d7c672c4ff..d1c3dc946486 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\n@@ -681,7 +681,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c,\n \t}\n \n \tINIT_WORK(&rq->am.work, mlx5e_rx_am_work);\n-\trq->am.mode = params->rx_cq_period_mode;\n+\trq->am.mode = params->rx_cq_moderation.cq_period_mode;\n \trq->page_cache.head = 0;\n \trq->page_cache.tail = 0;\n \n@@ -1974,7 +1974,7 @@ static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,\n \t}\n \n \tmlx5e_build_common_cq_param(priv, param);\n-\tparam->cq_period_mode = params->rx_cq_period_mode;\n+\tparam->cq_period_mode = params->rx_cq_moderation.cq_period_mode;\n }\n \n static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,\n@@ -1986,8 +1986,7 @@ static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,\n \tMLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);\n \n \tmlx5e_build_common_cq_param(priv, param);\n-\n-\tparam->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;\n+\tparam->cq_period_mode = params->tx_cq_moderation.cq_period_mode;\n }\n \n static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,\n@@ -3987,14 +3986,32 @@ static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)\n \t\t (pci_bw <= 16000) && (pci_bw < link_speed));\n }\n \n+void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)\n+{\n+\tparams->tx_cq_moderation.cq_period_mode = cq_period_mode;\n+\n+\tparams->tx_cq_moderation.pkts =\n+\t\tMLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;\n+\tparams->tx_cq_moderation.usec =\n+\t\tMLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;\n+\n+\tif (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)\n+\t\tparams->tx_cq_moderation.usec =\n+\t\t\tMLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;\n+\n+\tMLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,\n+\t\t\tparams->tx_cq_moderation.cq_period_mode ==\n+\t\t\t\tMLX5_CQ_PERIOD_MODE_START_FROM_CQE);\n+}\n+\n void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)\n {\n-\tparams->rx_cq_period_mode = cq_period_mode;\n+\tparams->rx_cq_moderation.cq_period_mode = cq_period_mode;\n \n \tparams->rx_cq_moderation.pkts =\n \t\tMLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;\n \tparams->rx_cq_moderation.usec =\n-\t\t\tMLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;\n+\t\tMLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;\n \n \tif (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)\n \t\tparams->rx_cq_moderation.usec =\n@@ -4002,10 +4019,11 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)\n \n \tif (params->rx_am_enabled)\n \t\tparams->rx_cq_moderation =\n-\t\t\tmlx5e_am_get_def_profile(params->rx_cq_period_mode);\n+\t\t\tmlx5e_am_get_def_profile(cq_period_mode);\n \n \tMLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,\n-\t\t\tparams->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);\n+\t\t\tparams->rx_cq_moderation.cq_period_mode ==\n+\t\t\t\tMLX5_CQ_PERIOD_MODE_START_FROM_CQE);\n }\n \n u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)\n@@ -4065,9 +4083,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,\n \t\t\tMLX5_CQ_PERIOD_MODE_START_FROM_EQE;\n \tparams->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);\n \tmlx5e_set_rx_cq_mode_params(params, cq_period_mode);\n-\n-\tparams->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;\n-\tparams->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;\n+\tmlx5e_set_tx_cq_mode_params(params, cq_period_mode);\n \n \t/* TX inline */\n \tparams->tx_max_inline = mlx5e_get_max_inline_cap(mdev);\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c\nindex acf32fe952cd..e401d9d245f3 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx_am.c\n@@ -63,7 +63,11 @@ profile[MLX5_CQ_PERIOD_NUM_MODES][MLX5E_PARAMS_AM_NUM_PROFILES] = {\n \n static inline struct mlx5e_cq_moder mlx5e_am_get_profile(u8 cq_period_mode, int ix)\n {\n-\treturn profile[cq_period_mode][ix];\n+\tstruct mlx5e_cq_moder cq_moder;\n+\n+\tcq_moder = profile[cq_period_mode][ix];\n+\tcq_moder.cq_period_mode = cq_period_mode;\n+\treturn cq_moder;\n }\n \n struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode)\n@@ -75,7 +79,7 @@ struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode)\n \telse /* MLX5_CQ_PERIOD_MODE_START_FROM_EQE */\n \t\tdefault_profile_ix = MLX5E_RX_AM_DEF_PROFILE_EQE;\n \n-\treturn profile[rx_cq_period_mode][default_profile_ix];\n+\treturn mlx5e_am_get_profile(rx_cq_period_mode, default_profile_ix);\n }\n \n /* Adaptive moderation logic */\n","prefixes":["net-next","12/12"]}