{"id":834173,"url":"http://patchwork.ozlabs.org/api/1.2/patches/834173/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20171104085030.25430-3-saeedm@mellanox.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/1.2/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171104085030.25430-3-saeedm@mellanox.com>","list_archive_url":null,"date":"2017-11-04T08:50:20","name":"[net-next,02/12] net/mlx5: QCAM register firmware command support","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"08a8d5ef46a939f47df4ac30f479acf4c925859a","submitter":{"id":65299,"url":"http://patchwork.ozlabs.org/api/1.2/people/65299/?format=json","name":"Saeed Mahameed","email":"saeedm@mellanox.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/1.2/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20171104085030.25430-3-saeedm@mellanox.com/mbox/","series":[{"id":11869,"url":"http://patchwork.ozlabs.org/api/1.2/series/11869/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=11869","date":"2017-11-04T08:50:18","name":"[net-next,01/12] net/dcb: Add dscp to priority selector type","version":1,"mbox":"http://patchwork.ozlabs.org/series/11869/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/834173/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/834173/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yTXd86WTqz9sBW\n\tfor ;\n\tSat, 4 Nov 2017 19:52:12 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1756247AbdKDIwD (ORCPT );\n\tSat, 4 Nov 2017 04:52:03 -0400","from mail-il-dmz.mellanox.com ([193.47.165.129]:54454 \"EHLO\n\tmellanox.co.il\" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org\n\twith ESMTP id S1751838AbdKDIwA (ORCPT\n\t); Sat, 4 Nov 2017 04:52:00 -0400","from Internal Mail-Server by MTLPINE1 (envelope-from\n\tsaeedm@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 4 Nov 2017 10:51:51 +0200","from mti-swat15.mti.labs.mlnx. (mti-swat15.mti.labs.mlnx\n\t[10.20.1.123])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id vA48pkiQ022678;\n\tSat, 4 Nov 2017 10:51:50 +0200"],"From":"Saeed Mahameed ","To":"\"David S. Miller\" ","Cc":"netdev@vger.kernel.org, Huy Nguyen ,\n\tSaeed Mahameed ","Subject":"[net-next 02/12] net/mlx5: QCAM register firmware command support","Date":"Sat, 4 Nov 2017 01:50:20 -0700","Message-Id":"<20171104085030.25430-3-saeedm@mellanox.com>","X-Mailer":"git-send-email 2.14.2","In-Reply-To":"<20171104085030.25430-1-saeedm@mellanox.com>","References":"<20171104085030.25430-1-saeedm@mellanox.com>","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"From: Huy Nguyen \n\nThe QCAM register provides capability bit for all the QoS registers\nusing ACCESS_REG command.\n\nSigned-off-by: Huy Nguyen \nReviewed-by: Parav Pandit \nSigned-off-by: Saeed Mahameed \n---\n drivers/net/ethernet/mellanox/mlx5/core/fw.c | 10 ++++++\n .../net/ethernet/mellanox/mlx5/core/mlx5_core.h | 2 ++\n drivers/net/ethernet/mellanox/mlx5/core/port.c | 12 +++++++\n include/linux/mlx5/device.h | 14 ++++++++\n include/linux/mlx5/driver.h | 2 ++\n include/linux/mlx5/mlx5_ifc.h | 40 +++++++++++++++++++++-\n 6 files changed, 79 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c\nindex 2c71557d1cee..5ef1b56b6a96 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c\n@@ -106,6 +106,13 @@ static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)\n \t\t\t\t MLX5_MCAM_REGS_FIRST_128);\n }\n \n+static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)\n+{\n+\treturn mlx5_query_qcam_reg(dev, dev->caps.qcam,\n+\t\t\t\t MLX5_QCAM_FEATURE_ENHANCED_FEATURES,\n+\t\t\t\t MLX5_QCAM_REGS_FIRST_128);\n+}\n+\n int mlx5_query_hca_caps(struct mlx5_core_dev *dev)\n {\n \tint err;\n@@ -182,6 +189,9 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)\n \tif (MLX5_CAP_GEN(dev, mcam_reg))\n \t\tmlx5_get_mcam_reg(dev);\n \n+\tif (MLX5_CAP_GEN(dev, qcam_reg))\n+\t\tmlx5_get_qcam_reg(dev);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h\nindex 8f00de2fe283..ff4a0b889a6f 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h\n@@ -122,6 +122,8 @@ int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,\n \t\t\tu8 access_reg_group);\n int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,\n \t\t\tu8 access_reg_group);\n+int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,\n+\t\t\tu8 feature_group, u8 access_reg_group);\n \n void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);\n void mlx5_lag_remove(struct mlx5_core_dev *dev);\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c\nindex e07061f565d6..b6553be841f9 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/port.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c\n@@ -98,6 +98,18 @@ int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,\n \treturn mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);\n }\n \n+int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,\n+\t\t\tu8 feature_group, u8 access_reg_group)\n+{\n+\tu32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};\n+\tint sz = MLX5_ST_SZ_BYTES(qcam_reg);\n+\n+\tMLX5_SET(qcam_reg, in, feature_group, feature_group);\n+\tMLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);\n+\n+\treturn mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);\n+}\n+\n struct mlx5_reg_pcap {\n \tu8\t\t\trsvd0;\n \tu8\t\t\tport_num;\ndiff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h\nindex e32dbc4934db..6d79b3f79458 100644\n--- a/include/linux/mlx5/device.h\n+++ b/include/linux/mlx5/device.h\n@@ -1000,6 +1000,14 @@ enum mlx5_mcam_feature_groups {\n \tMLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,\n };\n \n+enum mlx5_qcam_reg_groups {\n+\tMLX5_QCAM_REGS_FIRST_128 = 0x0,\n+};\n+\n+enum mlx5_qcam_feature_groups {\n+\tMLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,\n+};\n+\n /* GET Dev Caps macros */\n #define MLX5_CAP_GEN(mdev, cap) \\\n \tMLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)\n@@ -1108,6 +1116,12 @@ enum mlx5_mcam_feature_groups {\n #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \\\n \tMLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)\n \n+#define MLX5_CAP_QCAM_REG(mdev, fld) \\\n+\tMLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)\n+\n+#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \\\n+\tMLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)\n+\n #define MLX5_CAP_FPGA(mdev, cap) \\\n \tMLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)\n \ndiff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h\nindex 08c77b7e59cb..ed5be52282ea 100644\n--- a/include/linux/mlx5/driver.h\n+++ b/include/linux/mlx5/driver.h\n@@ -109,6 +109,7 @@ enum {\n enum {\n \tMLX5_REG_QETCR\t\t = 0x4005,\n \tMLX5_REG_QTCT\t\t = 0x400a,\n+\tMLX5_REG_QCAM = 0x4019,\n \tMLX5_REG_DCBX_PARAM = 0x4020,\n \tMLX5_REG_DCBX_APP = 0x4021,\n \tMLX5_REG_FPGA_CAP\t = 0x4022,\n@@ -798,6 +799,7 @@ struct mlx5_core_dev {\n \t\tu32 pcam[MLX5_ST_SZ_DW(pcam_reg)];\n \t\tu32 mcam[MLX5_ST_SZ_DW(mcam_reg)];\n \t\tu32 fpga[MLX5_ST_SZ_DW(fpga_cap)];\n+\t\tu32 qcam[MLX5_ST_SZ_DW(qcam_reg)];\n \t} caps;\n \tphys_addr_t\t\tiseg_base;\n \tstruct mlx5_init_seg __iomem *iseg;\ndiff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h\nindex 69772347f866..f127c5b310c5 100644\n--- a/include/linux/mlx5/mlx5_ifc.h\n+++ b/include/linux/mlx5/mlx5_ifc.h\n@@ -838,7 +838,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 cc_modify_allowed[0x1];\n \tu8 start_pad[0x1];\n \tu8 cache_line_128byte[0x1];\n-\tu8 reserved_at_165[0xb];\n+\tu8 reserved_at_165[0xa];\n+\tu8 qcam_reg[0x1];\n \tu8 gid_table_size[0x10];\n \n \tu8 out_of_seq_cnt[0x1];\n@@ -7890,6 +7891,43 @@ struct mlx5_ifc_mcam_reg_bits {\n \tu8 reserved_at_1c0[0x80];\n };\n \n+struct mlx5_ifc_qcam_access_reg_cap_mask {\n+\tu8 qcam_access_reg_cap_mask_127_to_20[0x6C];\n+\tu8 qpdpm[0x1];\n+\tu8 qcam_access_reg_cap_mask_18_to_4[0x0F];\n+\tu8 qdpm[0x1];\n+\tu8 qpts[0x1];\n+\tu8 qcap[0x1];\n+\tu8 qcam_access_reg_cap_mask_0[0x1];\n+};\n+\n+struct mlx5_ifc_qcam_qos_feature_cap_mask {\n+\tu8 qcam_qos_feature_cap_mask_127_to_1[0x7F];\n+\tu8 qpts_trust_both[0x1];\n+};\n+\n+struct mlx5_ifc_qcam_reg_bits {\n+\tu8 reserved_at_0[0x8];\n+\tu8 feature_group[0x8];\n+\tu8 reserved_at_10[0x8];\n+\tu8 access_reg_group[0x8];\n+\tu8 reserved_at_20[0x20];\n+\n+\tunion {\n+\t\tstruct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;\n+\t\tu8 reserved_at_0[0x80];\n+\t} qos_access_reg_cap_mask;\n+\n+\tu8 reserved_at_c0[0x80];\n+\n+\tunion {\n+\t\tstruct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;\n+\t\tu8 reserved_at_0[0x80];\n+\t} qos_feature_cap_mask;\n+\n+\tu8 reserved_at_1c0[0x80];\n+};\n+\n struct mlx5_ifc_pcap_reg_bits {\n \tu8 reserved_at_0[0x8];\n \tu8 local_port[0x8];\n","prefixes":["net-next","02/12"]}