{"id":833384,"url":"http://patchwork.ozlabs.org/api/1.2/patches/833384/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20171102143511.15910-1-Eugeniy.Paltsev@synopsys.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171102143511.15910-1-Eugeniy.Paltsev@synopsys.com>","list_archive_url":null,"date":"2017-11-02T14:35:11","name":"[U-Boot,v3] DW SPI: Get clock value from Device Tree","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"9543ff1537003baee2dedd6d74d51da43bb95928","submitter":{"id":69220,"url":"http://patchwork.ozlabs.org/api/1.2/people/69220/?format=json","name":"Eugeniy Paltsev","email":"Eugeniy.Paltsev@synopsys.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/1.2/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20171102143511.15910-1-Eugeniy.Paltsev@synopsys.com/mbox/","series":[{"id":11519,"url":"http://patchwork.ozlabs.org/api/1.2/series/11519/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=11519","date":"2017-11-02T14:35:11","name":"[U-Boot,v3] DW SPI: Get clock value from Device Tree","version":3,"mbox":"http://patchwork.ozlabs.org/series/11519/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/833384/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/833384/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySSLL1FNlz9sNw\n\tfor ;\n\tFri, 3 Nov 2017 01:35:36 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid B23E0C21D76; Thu, 2 Nov 2017 14:35:24 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 54FBFC21C45;\n\tThu, 2 Nov 2017 14:35:21 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid AB9E4C21C45; Thu, 2 Nov 2017 14:35:19 +0000 (UTC)","from smtprelay.synopsys.com (smtprelay.synopsys.com [198.182.47.9])\n\tby lists.denx.de (Postfix) with ESMTPS id CD6BBC21C26\n\tfor ; Thu, 2 Nov 2017 14:35:18 +0000 (UTC)","from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66])\n\tby smtprelay.synopsys.com (Postfix) with ESMTP id 0839024E1FBB;\n\tThu, 2 Nov 2017 07:35:16 -0700 (PDT)","from mailhost.synopsys.com (localhost [127.0.0.1])\n\tby mailhost.synopsys.com (Postfix) with ESMTP id 975794B4;\n\tThu, 2 Nov 2017 07:35:16 -0700 (PDT)","from localhost.internal.synopsys.com (unknown [10.121.8.106])\n\tby mailhost.synopsys.com (Postfix) with ESMTP id 358784AA;\n\tThu, 2 Nov 2017 07:35:14 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H4,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","From":"Eugeniy Paltsev ","To":"Jagan Teki ,\n\tMarek Vasut ","Date":"Thu, 2 Nov 2017 17:35:11 +0300","Message-Id":"<20171102143511.15910-1-Eugeniy.Paltsev@synopsys.com>","X-Mailer":"git-send-email 2.9.3","Cc":"u-boot@lists.denx.de, palmur3@gmail.com,\n\tEugeniy Paltsev ,\n\tuboot-snps-arc@synopsys.com","Subject":"[U-Boot] [PATCH v3] DW SPI: Get clock value from Device Tree","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Add option to set spi controller clock frequency via device tree\nusing standard clock bindings.\nOld way of setting spi controller clock frequency (via implementation\nof 'cm_get_spi_controller_clk_hz' function in platform specific code)\nremains supported for backward compatibility with targets which don't use\ngeneric clock framework.\n\nSigned-off-by: Eugeniy Paltsev \n---\n\nMarek, Jagan,\nHow about this implementation?\n\nAs both SOCFPGA_GEN5 and SOCFPGA_ARRIA10 don't use generic clock framework,\nwe can determine way of clock getting based on CONFIG_IS_ENABLED(CLK) macro.\n\nSo we don't need any weak functions / soc-specific ifdefs in driver / changes\nin SOCFPGA_* stuff.\n\n\nChanges v2->v3:\n * get rid of soc-specific ifdefs in driver.\n\nChanges v1->v2:\n * disable clock if we can't get the rate.\n * get rid of cm_get_spi_controller_clk_hz weak declaration.\n\n drivers/spi/designware_spi.c | 69 +++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 68 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c\nindex 5aa507b..ad64949 100644\n--- a/drivers/spi/designware_spi.c\n+++ b/drivers/spi/designware_spi.c\n@@ -11,6 +11,7 @@\n */\n \n #include \n+#include \n #include \n #include \n #include \n@@ -18,7 +19,13 @@\n #include \n #include \n #include \n+/*\n+ * Some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) which don't implement\n+ * generic clock framework and uses their clock_manager functions.\n+ */\n+#if !CONFIG_IS_ENABLED(OF_CONTROL) || !CONFIG_IS_ENABLED(CLK)\n #include \n+#endif\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -94,6 +101,7 @@ struct dw_spi_priv {\n \tvoid __iomem *regs;\n \tunsigned int freq;\t\t/* Default frequency */\n \tunsigned int mode;\n+\tunsigned long bus_clk_rate;\n \n \tint bits_per_word;\n \tu8 cs;\t\t\t/* chip select pin */\n@@ -176,14 +184,73 @@ static void spi_hw_init(struct dw_spi_priv *priv)\n \tdebug(\"%s: fifo_len=%d\\n\", __func__, priv->fifo_len);\n }\n \n+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)\n+static int dw_spi_of_get_clk(struct udevice *bus)\n+{\n+\tstruct dw_spi_priv *priv = dev_get_priv(bus);\n+\tstruct clk clk;\n+\tint ret;\n+\n+\tret = clk_get_by_index(bus, 0, &clk);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tret = clk_enable(&clk);\n+\tif (ret && ret != -ENOSYS)\n+\t\treturn ret;\n+\n+\tpriv->bus_clk_rate = clk_get_rate(&clk);\n+\tif (!priv->bus_clk_rate) {\n+\t\tclk_disable(&clk);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tclk_free(&clk);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static int dw_spi_get_clk(struct udevice *bus)\n+{\n+\tstruct dw_spi_priv *priv = dev_get_priv(bus);\n+\n+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)\n+\tint ret;\n+\n+\t/* Try to get clock frequency from device tree */\n+\tret = dw_spi_of_get_clk(bus);\n+\tif (ret)\n+\t\treturn ret;\n+#else\n+\t/*\n+\t * Some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't implement\n+\t * generic clock framework and use cm_get_spi_controller_clk_hz\n+\t * function (defined in asm/arch/clock_manager.h) to get spi controller\n+\t * clock frequency.\n+\t */\n+\tpriv->bus_clk_rate = cm_get_spi_controller_clk_hz();\n+#endif\n+\n+\tif (!priv->bus_clk_rate)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n static int dw_spi_probe(struct udevice *bus)\n {\n \tstruct dw_spi_platdata *plat = dev_get_platdata(bus);\n \tstruct dw_spi_priv *priv = dev_get_priv(bus);\n+\tint ret;\n \n \tpriv->regs = plat->regs;\n \tpriv->freq = plat->frequency;\n \n+\tret = dw_spi_get_clk(bus);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* Currently only bits_per_word == 8 supported */\n \tpriv->bits_per_word = 8;\n \n@@ -369,7 +436,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)\n \tspi_enable_chip(priv, 0);\n \n \t/* clk_div doesn't support odd number */\n-\tclk_div = cm_get_spi_controller_clk_hz() / speed;\n+\tclk_div = priv->bus_clk_rate / speed;\n \tclk_div = (clk_div + 1) & 0xfffe;\n \tdw_writel(priv, DW_SPI_BAUDR, clk_div);\n \n","prefixes":["U-Boot","v3"]}