{"id":833366,"url":"http://patchwork.ozlabs.org/api/1.2/patches/833366/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/20171102140501.87671-6-gwalbon@linux.vnet.ibm.com/","project":{"id":15,"url":"http://patchwork.ozlabs.org/api/1.2/projects/15/?format=json","name":"Ubuntu Kernel","link_name":"ubuntu-kernel","list_id":"kernel-team.lists.ubuntu.com","list_email":"kernel-team@lists.ubuntu.com","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171102140501.87671-6-gwalbon@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-11-02T14:04:54","name":"[Artful,05/12] powerpc/perf: Add thread IMC PMU support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e8ac5445e1ca3eb97d7095f8a1a75da8bbbe78be","submitter":{"id":71662,"url":"http://patchwork.ozlabs.org/api/1.2/people/71662/?format=json","name":"Gustavo Walbon","email":"gwalbon@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/20171102140501.87671-6-gwalbon@linux.vnet.ibm.com/mbox/","series":[{"id":11509,"url":"http://patchwork.ozlabs.org/api/1.2/series/11509/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=11509","date":"2017-11-02T14:04:50","name":"Backport for Power9 Nest PMU Instrumentation","version":1,"mbox":"http://patchwork.ozlabs.org/series/11509/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/833366/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/833366/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.ubuntu.com\n\t(client-ip=91.189.94.19; helo=huckleberry.canonical.com;\n\tenvelope-from=kernel-team-bounces@lists.ubuntu.com;\n\treceiver=)","Received":["from huckleberry.canonical.com (huckleberry.canonical.com\n\t[91.189.94.19])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySRgY0JDyz9t2M;\n\tFri, 3 Nov 2017 01:05:29 +1100 (AEDT)","from localhost ([127.0.0.1] helo=huckleberry.canonical.com)\n\tby huckleberry.canonical.com with esmtp (Exim 4.86_2)\n\t(envelope-from )\n\tid 1eAG7Y-0002Gg-76; Thu, 02 Nov 2017 14:05:24 +0000","from mx0a-001b2d01.pphosted.com ([148.163.156.1])\n\tby huckleberry.canonical.com with esmtps\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2)\n\t(envelope-from ) id 1eAG7V-0002B0-01\n\tfor kernel-team@lists.ubuntu.com; Thu, 02 Nov 2017 14:05:21 +0000","from pps.filterd (m0098404.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tvA2E4R44084018\n\tfor ; Thu, 2 Nov 2017 10:05:19 -0400","from e15.ny.us.ibm.com (e15.ny.us.ibm.com [129.33.205.205])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2dyynxtsxm-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 02 Nov 2017 10:05:18 -0400","from localhost\n\tby e15.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tThu, 2 Nov 2017 10:05:14 -0400","from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com\n\t[9.57.199.110])\n\tby b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid vA2E5E2p49283080; Thu, 2 Nov 2017 14:05:14 GMT","from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id B107AAE052;\n\tThu, 2 Nov 2017 10:06:00 -0400 (EDT)","from localhost (unknown [9.85.138.60])\n\tby b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 30E97AE056;\n\tThu, 2 Nov 2017 10:06:00 -0400 (EDT)"],"From":"Gustavo Walbon ","To":"kernel-team@lists.ubuntu.com","Subject":"[Artful][PATCH 05/12] powerpc/perf: Add thread IMC PMU support","Date":"Thu, 2 Nov 2017 12:04:54 -0200","X-Mailer":"git-send-email 2.13.3","In-Reply-To":"<20171102140501.87671-1-gwalbon@linux.vnet.ibm.com>","References":"<20171102140501.87671-1-gwalbon@linux.vnet.ibm.com>","X-TM-AS-GCONF":"00","x-cbid":"17110214-0036-0000-0000-00000285B79C","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007997; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000239; SDB=6.00940090; UDB=6.00474019;\n\tIPR=6.00720346; \n\tBA=6.00005666; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017836;\n\tXFM=3.00000015; UTC=2017-11-02 14:05:15","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17110214-0037-0000-0000-00004243B1B2","Message-Id":"<20171102140501.87671-6-gwalbon@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-11-02_05:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tpriorityscore=1501\n\tmalwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0\n\tclxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0\n\tclassifier=spam adjust=0 reason=mlx scancount=1\n\tengine=8.0.1-1707230000\n\tdefinitions=main-1711020178","X-BeenThere":"kernel-team@lists.ubuntu.com","X-Mailman-Version":"2.1.20","Precedence":"list","List-Id":"Kernel team discussions ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"kernel-team-bounces@lists.ubuntu.com","Sender":"\"kernel-team\" "},"content":"From: Anju T Sudhakar \n\nBugLink: https://bugs.launchpad.net/bugs/1481347\n\nAdd support to register Thread In-Memory Collection PMU counters.\nPatch adds thread IMC specific data structures, along with memory\ninit functions and CPU hotplug support.\n\nSigned-off-by: Anju T Sudhakar \nSigned-off-by: Hemant Kumar \nSigned-off-by: Madhavan Srinivasan \nSigned-off-by: Michael Ellerman \n(cherry-picked from f74c89bd80fb3f1328fdf4a44eeba793cdce4222)\nSigned-off-by: Gustavo Walbon \n---\n arch/powerpc/perf/imc-pmu.c | 270 +++++++++++++++++++++++++++++++++++++++++++-\n include/linux/cpuhotplug.h | 1 +\n 2 files changed, 267 insertions(+), 4 deletions(-)","diff":"diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c\nindex 482f8d6d5e65..46cd912af060 100644\n--- a/arch/powerpc/perf/imc-pmu.c\n+++ b/arch/powerpc/perf/imc-pmu.c\n@@ -37,6 +37,12 @@ static cpumask_t core_imc_cpumask;\n struct imc_pmu_ref *core_imc_refc;\n static struct imc_pmu *core_imc_pmu;\n \n+/* Thread IMC data structures and variables */\n+\n+static DEFINE_PER_CPU(u64 *, thread_imc_mem);\n+static struct imc_pmu *thread_imc_pmu;\n+static int thread_imc_mem_size;\n+\n struct imc_pmu *imc_event_to_pmu(struct perf_event *event)\n {\n \treturn container_of(event->pmu, struct imc_pmu, pmu);\n@@ -728,15 +734,188 @@ static int core_imc_event_init(struct perf_event *event)\n \treturn 0;\n }\n \n-static u64 * get_event_base_addr(struct perf_event *event)\n+/*\n+ * Allocates a page of memory for each of the online cpus, and write the\n+ * physical base address of that page to the LDBAR for that cpu.\n+ *\n+ * LDBAR Register Layout:\n+ *\n+ * 0 4 8 12 16 20 24 28\n+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |\n+ * | | [ ] [ Counter Address [8:50]\n+ * | * Mode |\n+ * | * PB Scope\n+ * * Enable/Disable\n+ *\n+ * 32 36 40 44 48 52 56 60\n+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |\n+ * Counter Address [8:50] ]\n+ *\n+ */\n+static int thread_imc_mem_alloc(int cpu_id, int size)\n+{\n+\tu64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id);\n+\tint phys_id = topology_physical_package_id(cpu_id);\n+\n+\tif (!local_mem) {\n+\t\t/*\n+\t\t * This case could happen only once at start, since we dont\n+\t\t * free the memory in cpu offline path.\n+\t\t */\n+\t\tlocal_mem = page_address(alloc_pages_node(phys_id,\n+\t\t\t\t GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE,\n+\t\t\t\t get_order(size)));\n+\t\tif (!local_mem)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tper_cpu(thread_imc_mem, cpu_id) = local_mem;\n+\t}\n+\n+\tldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;\n+\n+\tmtspr(SPRN_LDBAR, ldbar_value);\n+\treturn 0;\n+}\n+\n+static int ppc_thread_imc_cpu_online(unsigned int cpu)\n {\n+\treturn thread_imc_mem_alloc(cpu, thread_imc_mem_size);\n+}\n+\n+static int ppc_thread_imc_cpu_offline(unsigned int cpu)\n+{\n+\tmtspr(SPRN_LDBAR, 0);\n+\treturn 0;\n+}\n+\n+static int thread_imc_cpu_init(void)\n+{\n+\treturn cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,\n+\t\t\t \"perf/powerpc/imc_thread:online\",\n+\t\t\t ppc_thread_imc_cpu_online,\n+\t\t\t ppc_thread_imc_cpu_offline);\n+}\n+\n+void thread_imc_pmu_sched_task(struct perf_event_context *ctx,\n+\t\t\t\t bool sched_in)\n+{\n+\tint core_id;\n+\tstruct imc_pmu_ref *ref;\n+\n+\tif (!is_core_imc_mem_inited(smp_processor_id()))\n+\t\treturn;\n+\n+\tcore_id = smp_processor_id() / threads_per_core;\n \t/*\n-\t * Subsequent patch will add code to detect caller imc pmu\n-\t * and return accordingly.\n+\t * imc pmus are enabled only when it is used.\n+\t * See if this is triggered for the first time.\n+\t * If yes, take the mutex lock and enable the counters.\n+\t * If not, just increment the count in ref count struct.\n \t */\n+\tref = &core_imc_refc[core_id];\n+\tif (!ref)\n+\t\treturn;\n+\n+\tif (sched_in) {\n+\t\tmutex_lock(&ref->lock);\n+\t\tif (ref->refc == 0) {\n+\t\t\tif (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,\n+\t\t\t get_hard_smp_processor_id(smp_processor_id()))) {\n+\t\t\t\tmutex_unlock(&ref->lock);\n+\t\t\t\tpr_err(\"thread-imc: Unable to start the counter\\\n+\t\t\t\t\t\t\tfor core %d\\n\", core_id);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+\t\t++ref->refc;\n+\t\tmutex_unlock(&ref->lock);\n+\t} else {\n+\t\tmutex_lock(&ref->lock);\n+\t\tref->refc--;\n+\t\tif (ref->refc == 0) {\n+\t\t\tif (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,\n+\t\t\t get_hard_smp_processor_id(smp_processor_id()))) {\n+\t\t\t\tmutex_unlock(&ref->lock);\n+\t\t\t\tpr_err(\"thread-imc: Unable to stop the counters\\\n+\t\t\t\t\t\t\tfor core %d\\n\", core_id);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t} else if (ref->refc < 0) {\n+\t\t\tref->refc = 0;\n+\t\t}\n+\t\tmutex_unlock(&ref->lock);\n+\t}\n+\n+\treturn;\n+}\n+\n+static int thread_imc_event_init(struct perf_event *event)\n+{\n+\tu32 config = event->attr.config;\n+\tstruct task_struct *target;\n+\tstruct imc_pmu *pmu;\n+\n+\tif (event->attr.type != event->pmu->type)\n+\t\treturn -ENOENT;\n+\n+\t/* Sampling not supported */\n+\tif (event->hw.sample_period)\n+\t\treturn -EINVAL;\n+\n+\tevent->hw.idx = -1;\n+\tpmu = imc_event_to_pmu(event);\n+\n+\t/* Sanity check for config offset */\n+\tif (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))\n+\t\treturn -EINVAL;\n+\n+\ttarget = event->hw.target;\n+\tif (!target)\n+\t\treturn -EINVAL;\n+\n+\tevent->pmu->task_ctx_nr = perf_sw_context;\n+\treturn 0;\n+}\n+\n+static bool is_thread_imc_pmu(struct perf_event *event)\n+{\n+\tif (!strncmp(event->pmu->name, \"thread_imc\", strlen(\"thread_imc\")))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static u64 * get_event_base_addr(struct perf_event *event)\n+{\n+\tu64 addr;\n+\n+\tif (is_thread_imc_pmu(event)) {\n+\t\taddr = (u64)per_cpu(thread_imc_mem, smp_processor_id());\n+\t\treturn (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));\n+\t}\n+\n \treturn (u64 *)event->hw.event_base;\n }\n \n+static void thread_imc_pmu_start_txn(struct pmu *pmu,\n+\t\t\t\t unsigned int txn_flags)\n+{\n+\tif (txn_flags & ~PERF_PMU_TXN_ADD)\n+\t\treturn;\n+\tperf_pmu_disable(pmu);\n+}\n+\n+static void thread_imc_pmu_cancel_txn(struct pmu *pmu)\n+{\n+\tperf_pmu_enable(pmu);\n+}\n+\n+static int thread_imc_pmu_commit_txn(struct pmu *pmu)\n+{\n+\tperf_pmu_enable(pmu);\n+\treturn 0;\n+}\n+\n static u64 imc_read_counter(struct perf_event *event)\n {\n \tu64 *addr, data;\n@@ -794,6 +973,26 @@ static int imc_event_add(struct perf_event *event, int flags)\n \treturn 0;\n }\n \n+static int thread_imc_event_add(struct perf_event *event, int flags)\n+{\n+\tif (flags & PERF_EF_START)\n+\t\timc_event_start(event, flags);\n+\n+\t/* Enable the sched_task to start the engine */\n+\tperf_sched_cb_inc(event->ctx->pmu);\n+\treturn 0;\n+}\n+\n+static void thread_imc_event_del(struct perf_event *event, int flags)\n+{\n+\t/*\n+\t * Take a snapshot and calculate the delta and update\n+\t * the event counter values.\n+\t */\n+\timc_event_update(event);\n+\tperf_sched_cb_dec(event->ctx->pmu);\n+}\n+\n /* update_pmu_ops : Populate the appropriate operations for \"pmu\" */\n static int update_pmu_ops(struct imc_pmu *pmu)\n {\n@@ -815,6 +1014,15 @@ static int update_pmu_ops(struct imc_pmu *pmu)\n \t\tpmu->pmu.event_init = core_imc_event_init;\n \t\tpmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;\n \t\tbreak;\n+\tcase IMC_DOMAIN_THREAD:\n+\t\tpmu->pmu.event_init = thread_imc_event_init;\n+\t\tpmu->pmu.sched_task = thread_imc_pmu_sched_task;\n+\t\tpmu->pmu.add = thread_imc_event_add;\n+\t\tpmu->pmu.del = thread_imc_event_del;\n+\t\tpmu->pmu.start_txn = thread_imc_pmu_start_txn;\n+\t\tpmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;\n+\t\tpmu->pmu.commit_txn = thread_imc_pmu_commit_txn;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -882,6 +1090,31 @@ static void cleanup_all_core_imc_memory(void)\n \tkfree(core_imc_refc);\n }\n \n+static void thread_imc_ldbar_disable(void *dummy)\n+{\n+\t/*\n+\t * By Zeroing LDBAR, we disable thread-imc\n+\t * updates.\n+\t */\n+\tmtspr(SPRN_LDBAR, 0);\n+}\n+\n+void thread_imc_disable(void)\n+{\n+\ton_each_cpu(thread_imc_ldbar_disable, NULL, 1);\n+}\n+\n+static void cleanup_all_thread_imc_memory(void)\n+{\n+\tint i, order = get_order(thread_imc_mem_size);\n+\n+\tfor_each_online_cpu(i) {\n+\t\tif (per_cpu(thread_imc_mem, i))\n+\t\t\tfree_pages((u64)per_cpu(thread_imc_mem, i), order);\n+\n+\t}\n+}\n+\n /*\n * Common function to unregister cpu hotplug callback and\n * free the memory.\n@@ -908,6 +1141,12 @@ static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)\n \t\tcleanup_all_core_imc_memory();\n \t}\n \n+\t/* Free thread_imc memory */\n+\tif (pmu_ptr->domain == IMC_DOMAIN_THREAD) {\n+\t\tcpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);\n+\t\tcleanup_all_thread_imc_memory();\n+\t}\n+\n \t/* Only free the attr_groups which are dynamically allocated */\n \tkfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);\n \tkfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);\n@@ -923,7 +1162,7 @@ static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,\n \t\t\t\t\t\t\t\tint pmu_index)\n {\n \tconst char *s;\n-\tint nr_cores;\n+\tint nr_cores, cpu, res;\n \n \tif (of_property_read_string(parent, \"name\", &s))\n \t\treturn -ENODEV;\n@@ -959,6 +1198,21 @@ static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,\n \n \t\tcore_imc_pmu = pmu_ptr;\n \t\tbreak;\n+\tcase IMC_DOMAIN_THREAD:\n+\t\t/* Update the pmu name */\n+\t\tpmu_ptr->pmu.name = kasprintf(GFP_KERNEL, \"%s%s\", s, \"_imc\");\n+\t\tif (!pmu_ptr->pmu.name)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tthread_imc_mem_size = pmu_ptr->counter_mem_size;\n+\t\tfor_each_online_cpu(cpu) {\n+\t\t\tres = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);\n+\t\t\tif (res)\n+\t\t\t\treturn res;\n+\t\t}\n+\n+\t\tthread_imc_pmu = pmu_ptr;\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n@@ -1017,6 +1271,14 @@ int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_id\n \t\t}\n \n \t\tbreak;\n+\tcase IMC_DOMAIN_THREAD:\n+\t\tret = thread_imc_cpu_init();\n+\t\tif (ret) {\n+\t\t\tcleanup_all_thread_imc_memory();\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tbreak;\n \tdefault:\n \t\treturn -1;\t/* Unknown domain */\n \t}\ndiff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h\nindex 47eb6a1f2db9..f24bfb2b9a2d 100644\n--- a/include/linux/cpuhotplug.h\n+++ b/include/linux/cpuhotplug.h\n@@ -139,6 +139,7 @@ enum cpuhp_state {\n \tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,\n \tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,\n \tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,\n+\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,\n \tCPUHP_AP_WORKQUEUE_ONLINE,\n \tCPUHP_AP_RCUTREE_ONLINE,\n \tCPUHP_AP_ONLINE_DYN,\n","prefixes":["Artful","05/12"]}