{"id":833331,"url":"http://patchwork.ozlabs.org/api/1.2/patches/833331/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/1509625835-22344-4-git-send-email-claziss@synopsys.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.2/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509625835-22344-4-git-send-email-claziss@synopsys.com>","list_archive_url":null,"date":"2017-11-02T12:30:32","name":"[3/6,ARC] Add support for \"register file 16\" reduced register set","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8ce18c471815e8a0973aa974a4bf4ecd7114c5b3","submitter":{"id":67086,"url":"http://patchwork.ozlabs.org/api/1.2/people/67086/?format=json","name":"Claudiu Zissulescu","email":"Claudiu.Zissulescu@synopsys.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/1509625835-22344-4-git-send-email-claziss@synopsys.com/mbox/","series":[{"id":11495,"url":"http://patchwork.ozlabs.org/api/1.2/series/11495/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=11495","date":"2017-11-02T12:30:29","name":"New baremetal features and fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/11495/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/833331/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/833331/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-465737-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"whLcj3MU\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ySPh339B1z9sBW\n\tfor ;\n\tThu, 2 Nov 2017 23:35:47 +1100 (AEDT)","(qmail 54743 invoked by alias); 2 Nov 2017 12:34:46 -0000","(qmail 54104 invoked by uid 89); 2 Nov 2017 12:34:44 -0000","from us01smtprelay-2.synopsys.com (HELO smtprelay.synopsys.com)\n\t(198.182.60.111) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tThu, 02 Nov 2017 12:34:36 +0000","from mailhost.synopsys.com (mailhost3.synopsys.com\n\t[10.12.238.238])\tby smtprelay.synopsys.com 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ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-23.8 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=jd, barrel,\n\tHx-spam-relays-external:sk:US01WEH,\n\tHx-spam-relays-external:sk:us01weh","X-HELO":"smtprelay.synopsys.com","From":"Claudiu Zissulescu ","To":"","CC":", ,\n\t","Subject":"[PATCH 3/6] [ARC] Add support for \"register file 16\" reduced\n\tregister set","Date":"Thu, 2 Nov 2017 13:30:32 +0100","Message-ID":"<1509625835-22344-4-git-send-email-claziss@synopsys.com>","In-Reply-To":"<1509625835-22344-1-git-send-email-claziss@synopsys.com>","References":"<1509625835-22344-1-git-send-email-claziss@synopsys.com>","MIME-Version":"1.0","Content-Type":"text/plain"},"content":"gcc/\n2017-03-20 Claudiu Zissulescu \n\n\t* config/arc/arc-arches.def: Option mrf16 valid for all\n\tarchitectures.\n\t* config/arc/arc-c.def (__ARC_RF16__): New predefined macro.\n\t* config/arc/arc-cpus.def (em_mini): New cpu with rf16 on.\n\t* config/arc/arc-options.def (FL_RF16): Add mrf16 option.\n\t* config/arc/arc-tables.opt: Regenerate.\n\t* config/arc/arc.c (arc_conditional_register_usage): Handle\n\treduced register file case.\n\t(arc_file_start): Set must have build attributes.\n\t* config/arc/arc.h (MAX_ARC_PARM_REGS): Conditional define using\n\tmrf16 option value.\n\t* config/arc/arc.opt (mrf16): Add new option.\n\t* config/arc/elf.h (ATTRIBUTE_PCS): Define.\n\t* config/arc/genmultilib.awk: Handle new mrf16 option.\n\t* config/arc/linux.h (ATTRIBUTE_PCS): Define.\n\t* config/arc/t-multilib: Regenerate.\n\t* doc/invoke.texi (ARC Options): Document mrf16 option.\n\ngcc/testsuite/\n2017-03-20 Claudiu Zissulescu \n\n\t* gcc.dg/builtin-apply2.c: Change for the ARC's reduced register\n\tset file case.\n\nlibgcc/\n2017-09-18 Claudiu Zissulescu \n\n\t* config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16\n\toption.\n\t(__divsi3): Use RF16 safe registers.\n\t(__modsi3): Likewise.\n---\n gcc/config/arc/arc-arches.def | 8 ++++----\n gcc/config/arc/arc-c.def | 1 +\n gcc/config/arc/arc-cpus.def | 1 +\n gcc/config/arc/arc-options.def | 2 +-\n gcc/config/arc/arc-tables.opt | 3 +++\n gcc/config/arc/arc.c | 27 +++++++++++++++++++++++++++\n gcc/config/arc/arc.h | 2 +-\n gcc/config/arc/arc.opt | 4 ++++\n gcc/config/arc/elf.h | 4 ++++\n gcc/config/arc/genmultilib.awk | 2 ++\n gcc/config/arc/linux.h | 9 +++++++++\n gcc/config/arc/t-multilib | 4 ++--\n gcc/doc/invoke.texi | 8 +++++++-\n gcc/testsuite/gcc.dg/builtin-apply2.c | 8 +++++++-\n libgcc/config/arc/lib1funcs.S | 22 +++++++++++-----------\n 15 files changed, 84 insertions(+), 21 deletions(-)","diff":"diff --git a/gcc/config/arc/arc-arches.def b/gcc/config/arc/arc-arches.def\nindex 29cb9c4..a0d585b 100644\n--- a/gcc/config/arc/arc-arches.def\n+++ b/gcc/config/arc/arc-arches.def\n@@ -40,15 +40,15 @@\n \n ARC_ARCH (\"arcem\", em, FL_MPYOPT_1_6 | FL_DIVREM | FL_CD | FL_NORM\t\\\n \t | FL_BS | FL_SWAP | FL_FPUS | FL_SPFP | FL_DPFP\t\t\\\n-\t | FL_SIMD | FL_FPUDA | FL_QUARK, 0)\n+\t | FL_SIMD | FL_FPUDA | FL_QUARK | FL_RF16, 0)\n ARC_ARCH (\"archs\", hs, FL_MPYOPT_7_9 | FL_DIVREM | FL_NORM | FL_CD\t\\\n \t | FL_ATOMIC | FL_LL64 | FL_BS | FL_SWAP\t\t\t\\\n-\t | FL_FPUS | FL_FPUD,\t\t\t\t\t\t\\\n+\t | FL_FPUS | FL_FPUD | FL_RF16,\t\t\t\t\\\n \t FL_CD | FL_ATOMIC | FL_BS | FL_NORM | FL_SWAP)\n ARC_ARCH (\"arc6xx\", 6xx, FL_BS | FL_NORM | FL_SWAP | FL_MUL64 | FL_MUL32x16 \\\n-\t | FL_SPFP | FL_ARGONAUT | FL_DPFP, 0)\n+\t | FL_SPFP | FL_ARGONAUT | FL_DPFP | FL_RF16, 0)\n ARC_ARCH (\"arc700\", 700, FL_ATOMIC | FL_BS | FL_NORM | FL_SWAP | FL_EA \\\n-\t | FL_SIMD | FL_SPFP | FL_ARGONAUT | FL_DPFP,\t\t \\\n+\t | FL_SIMD | FL_SPFP | FL_ARGONAUT | FL_DPFP | FL_RF16, \\\n \t FL_BS | FL_NORM | FL_SWAP)\n \n /* Local Variables: */\ndiff --git a/gcc/config/arc/arc-c.def b/gcc/config/arc/arc-c.def\nindex 8c5097e..c9443c9 100644\n--- a/gcc/config/arc/arc-c.def\n+++ b/gcc/config/arc/arc-c.def\n@@ -28,6 +28,7 @@ ARC_C_DEF (\"__ARC_NORM__\",\tTARGET_NORM)\n ARC_C_DEF (\"__ARC_MUL64__\",\tTARGET_MUL64_SET)\n ARC_C_DEF (\"__ARC_MUL32BY16__\", TARGET_MULMAC_32BY16_SET)\n ARC_C_DEF (\"__ARC_SIMD__\",\tTARGET_SIMD_SET)\n+ARC_C_DEF (\"__ARC_RF16__\",\tTARGET_RF16)\n \n ARC_C_DEF (\"__ARC_BARREL_SHIFTER__\", TARGET_BARREL_SHIFTER)\n \ndiff --git a/gcc/config/arc/arc-cpus.def b/gcc/config/arc/arc-cpus.def\nindex 60b4045..c2b0062 100644\n--- a/gcc/config/arc/arc-cpus.def\n+++ b/gcc/config/arc/arc-cpus.def\n@@ -46,6 +46,7 @@\n TUNE\t Tune value for the given configuration, otherwise NONE. */\n \n ARC_CPU (em,\t em, 0, NONE)\n+ARC_CPU (em_mini, em, FL_RF16, NONE)\n ARC_CPU (arcem,\t em, FL_MPYOPT_2|FL_CD|FL_BS, NONE)\n ARC_CPU (em4,\t em, FL_CD, NONE)\n ARC_CPU (em4_dmips, em, FL_MPYOPT_2|FL_CD|FL_DIVREM|FL_NORM|FL_SWAP|FL_BS, NONE)\ndiff --git a/gcc/config/arc/arc-options.def b/gcc/config/arc/arc-options.def\nindex be51614..8fc7b50 100644\n--- a/gcc/config/arc/arc-options.def\n+++ b/gcc/config/arc/arc-options.def\n@@ -60,7 +60,7 @@\n ARC_OPT (FL_CD,\t (1ULL << 0), MASK_CODE_DENSITY,\t \"code density\")\n ARC_OPT (FL_DIVREM, (1ULL << 1), MASK_DIVREM,\t\t \"div/rem\")\n ARC_OPT (FL_NORM, (1ULL << 2), MASK_NORM_SET,\t \"norm\")\n-\n+ARC_OPT (FL_RF16, (1ULL << 3), MASK_RF16, \"rf16\")\n ARC_OPT (FL_ATOMIC, (1ULL << 4), MASK_ATOMIC,\t\t \"atomic\")\n ARC_OPT (FL_LL64, (1ULL << 5), MASK_LL64,\t\t \"double load/store\")\n ARC_OPT (FL_BS,\t (1ULL << 6), MASK_BARREL_SHIFTER,\t \"barrel shifter\")\ndiff --git a/gcc/config/arc/arc-tables.opt b/gcc/config/arc/arc-tables.opt\nindex ce23a52..21fc2d3 100644\n--- a/gcc/config/arc/arc-tables.opt\n+++ b/gcc/config/arc/arc-tables.opt\n@@ -28,6 +28,9 @@ EnumValue\n Enum(processor_type) String(em) Value(PROCESSOR_em)\n \n EnumValue\n+Enum(processor_type) String(em_mini) Value(PROCESSOR_em_mini)\n+\n+EnumValue\n Enum(processor_type) String(arcem) Value(PROCESSOR_arcem)\n \n EnumValue\ndiff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c\nindex 9867e6e..e7194a2 100644\n--- a/gcc/config/arc/arc.c\n+++ b/gcc/config/arc/arc.c\n@@ -1741,6 +1741,19 @@ arc_conditional_register_usage (void)\n \treg_alloc_order [i] = i;\n }\n \n+ /* Reduced configuration: don't use r4-r9, r16-r25. */\n+ if (TARGET_RF16)\n+ {\n+ for (i = 4; i <= 9; i++)\n+\t{\n+\t fixed_regs[i] = call_used_regs[i] = 1;\n+\t}\n+ for (i = 16; i <= 25; i++)\n+\t{\n+\t fixed_regs[i] = call_used_regs[i] = 1;\n+\t}\n+ }\n+\n for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)\n if (!call_used_regs[regno])\n CLEAR_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);\n@@ -5125,6 +5138,20 @@ static void arc_file_start (void)\n {\n default_file_start ();\n fprintf (asm_out_file, \"\\t.cpu %s\\n\", arc_cpu_string);\n+\n+ /* Set some want to have build attributes. */\n+ asm_fprintf (asm_out_file, \"\\t.arc_attribute Tag_ARC_PCS_config, %d\\n\",\n+\t ATTRIBUTE_PCS);\n+ asm_fprintf (asm_out_file, \"\\t.arc_attribute Tag_ARC_ABI_rf16, %d\\n\",\n+\t TARGET_RF16 ? 1 : 0);\n+ asm_fprintf (asm_out_file, \"\\t.arc_attribute Tag_ARC_ABI_pic, %d\\n\",\n+\t flag_pic ? 2 : 0);\n+ asm_fprintf (asm_out_file, \"\\t.arc_attribute Tag_ARC_ABI_tls, %d\\n\",\n+\t (arc_tp_regno != -1) ? 1 : 0);\n+ asm_fprintf (asm_out_file, \"\\t.arc_attribute Tag_ARC_ABI_sda, %d\\n\",\n+\t TARGET_NO_SDATA_SET ? 0 : 2);\n+ asm_fprintf (asm_out_file, \"\\t.arc_attribute Tag_ARC_ABI_exceptions, %d\\n\",\n+\t TARGET_OPTFPE ? 1 : 0);\n }\n \n /* Implement `TARGET_ASM_FILE_END'. */\ndiff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h\nindex ab12413..de211e2 100644\n--- a/gcc/config/arc/arc.h\n+++ b/gcc/config/arc/arc.h\n@@ -727,7 +727,7 @@ arc_return_addr_rtx(COUNT,FRAME)\n ((CUM) = 0)\n \n /* The number of registers used for parameter passing. Local to this file. */\n-#define MAX_ARC_PARM_REGS 8\n+#define MAX_ARC_PARM_REGS (TARGET_RF16 ? 4 : 8)\n \n /* 1 if N is a possible register number for function argument passing. */\n #define FUNCTION_ARG_REGNO_P(N) \\\ndiff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt\nindex 9baaf77..aacb599 100644\n--- a/gcc/config/arc/arc.opt\n+++ b/gcc/config/arc/arc.opt\n@@ -523,3 +523,7 @@ Enum(arc_lpc) String(28) Value(28)\n \n EnumValue\n Enum(arc_lpc) String(32) Value(32)\n+\n+mrf16\n+Target Report Mask(RF16)\n+Enable 16-entry register file.\ndiff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h\nindex 175e9fd..288a845 100644\n--- a/gcc/config/arc/elf.h\n+++ b/gcc/config/arc/elf.h\n@@ -67,5 +67,9 @@ along with GCC; see the file COPYING3. If not see\n #undef TARGET_AUTO_MODIFY_REG_DEFAULT\n #define TARGET_AUTO_MODIFY_REG_DEFAULT 1\n \n+/* Build attribute: procedure call standard. */\n+#undef ATTRIBUTE_PCS\n+#define ATTRIBUTE_PCS 2\n+\n #undef TARGET_ASM_FILE_END\n #define TARGET_ASM_FILE_END arc_file_end\ndiff --git a/gcc/config/arc/genmultilib.awk b/gcc/config/arc/genmultilib.awk\nindex 2734adc..3266bb0 100644\n--- a/gcc/config/arc/genmultilib.awk\n+++ b/gcc/config/arc/genmultilib.awk\n@@ -130,6 +130,8 @@ BEGIN {\n \t line = line \"/spfp\"\n \t else if (cpu_flg[i] == \"FL_DPFP\")\n \t line = line \"/dpfp\"\n+\t else if (cpu_flg[i] == \"FL_RF16\")\n+\t line = line \"/mrf16\"\n \t else\n \t {\n \t print \"Don't know the flag \" cpu_flg[i] > \"/dev/stderr\"\ndiff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h\nindex 8abc2c6..5099391 100644\n--- a/gcc/config/arc/linux.h\n+++ b/gcc/config/arc/linux.h\n@@ -92,3 +92,12 @@ along with GCC; see the file COPYING3. If not see\n /* Pre/post modify with register displacement are default off. */\n #undef TARGET_AUTO_MODIFY_REG_DEFAULT\n #define TARGET_AUTO_MODIFY_REG_DEFAULT 0\n+\n+#undef SUBTARGET_CPP_SPEC\n+#define SUBTARGET_CPP_SPEC \"\\\n+ %{pthread:-D_REENTRANT} \\\n+\"\n+\n+/* Build attribute: procedure call standard. */\n+#undef ATTRIBUTE_PCS\n+#define ATTRIBUTE_PCS 3\ndiff --git a/gcc/config/arc/t-multilib b/gcc/config/arc/t-multilib\nindex 9ffd4a6..eb1d8e3 100644\n--- a/gcc/config/arc/t-multilib\n+++ b/gcc/config/arc/t-multilib\n@@ -21,9 +21,9 @@\n # along with GCC; see the file COPYING3. If not see\n # .\n \n-MULTILIB_OPTIONS = mcpu=em/mcpu=arcem/mcpu=em4/mcpu=em4_dmips/mcpu=em4_fpus/mcpu=em4_fpuda/mcpu=quarkse_em/mcpu=hs/mcpu=archs/mcpu=hs34/mcpu=hs38/mcpu=hs38_linux/mcpu=arc600/mcpu=arc600_norm/mcpu=arc600_mul64/mcpu=arc600_mul32x16/mcpu=arc601/mcpu=arc601_norm/mcpu=arc601_mul64/mcpu=arc601_mul32x16/mcpu=arc700/mcpu=nps400\n+MULTILIB_OPTIONS = mcpu=em/mcpu=em_mini/mcpu=arcem/mcpu=em4/mcpu=em4_dmips/mcpu=em4_fpus/mcpu=em4_fpuda/mcpu=quarkse_em/mcpu=hs/mcpu=archs/mcpu=hs34/mcpu=hs38/mcpu=hs38_linux/mcpu=hs4x/mcpu=hs4xd/mcpu=arc600/mcpu=arc600_norm/mcpu=arc600_mul64/mcpu=arc600_mul32x16/mcpu=arc601/mcpu=arc601_norm/mcpu=arc601_mul64/mcpu=arc601_mul32x16/mcpu=arc700/mcpu=nps400\n \n-MULTILIB_DIRNAMES = em arcem em4 em4_dmips em4_fpus em4_fpuda quarkse_em hs archs hs34 hs38 hs38_linux arc600 arc600_norm arc600_mul64 arc600_mul32x16 arc601 arc601_norm arc601_mul64 arc601_mul32x16 arc700 nps400\n+MULTILIB_DIRNAMES = em em_mini arcem em4 em4_dmips em4_fpus em4_fpuda quarkse_em hs archs hs34 hs38 hs38_linux hs4x hs4xd arc600 arc600_norm arc600_mul64 arc600_mul32x16 arc601 arc601_norm arc601_mul64 arc601_mul32x16 arc700 nps400\n \n # Aliases:\n MULTILIB_MATCHES = mcpu?arc600=mcpu?ARC600\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 041be9a..409f9be 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -625,7 +625,7 @@ Objective-C and Objective-C++ Dialects}.\n -mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol\n -mtune=@var{cpu} -mmultcost=@var{num} @gol\n -munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol\n--mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu}}\n+-mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16}\n \n @emph{ARM Options}\n @gccoptlist{-mapcs-frame -mno-apcs-frame @gol\n@@ -14969,6 +14969,12 @@ specified, the compiler and run-time library might continue to use the\n loop mechanism for various needs. This option defines macro\n @code{__ARC_LPC_WIDTH__} with the value of @var{width}.\n \n+@item -mrf16\n+@opindex mrf16\n+This option instructs the compiler to generate code for a 16-entry\n+register file. This option defines the @code{__ARC_RF16__}\n+preprocessor macro.\n+\n @end table\n \n The following options are passed through to the assembler, and also\ndiff --git a/gcc/testsuite/gcc.dg/builtin-apply2.c b/gcc/testsuite/gcc.dg/builtin-apply2.c\nindex 3768caa..d811272 100644\n--- a/gcc/testsuite/gcc.dg/builtin-apply2.c\n+++ b/gcc/testsuite/gcc.dg/builtin-apply2.c\n@@ -19,9 +19,15 @@\n E, F and G are passed on stack. So the size of the stack argument\n data is 20. */\n #define STACK_ARGUMENTS_SIZE 20\n-#elif defined __MMIX__ || defined __arc__\n+#elif defined __MMIX__\n /* No parameters on stack for bar. */\n #define STACK_ARGUMENTS_SIZE 0\n+#elif defined __arc__\n+# ifdef __ARC_RF16__\n+# define STACK_ARGUMENTS_SIZE 4*4\n+# else\n+# define STACK_ARGUMENTS_SIZE 0\n+# endif\n #else\n #define STACK_ARGUMENTS_SIZE 64\n #endif\ndiff --git a/libgcc/config/arc/lib1funcs.S b/libgcc/config/arc/lib1funcs.S\nindex c3127ad..08e1510 100644\n--- a/libgcc/config/arc/lib1funcs.S\n+++ b/libgcc/config/arc/lib1funcs.S\n@@ -370,7 +370,7 @@ SYM(__udivmodsi4):\n \tmov_s\tr0,1\n \tj_s.d\t[blink]\n \tmov.c\tr0,0\n-#elif !defined (__OPTIMIZE_SIZE__)\n+#elif !defined (__OPTIMIZE_SIZE__) && !defined (__ARC_RF16__)\n #if defined (__ARC_NORM__) && defined (__ARC_BARREL_SHIFTER__)\n \tlsr_s r2,r0\n \tbrhs.d r1,r2,.Lret0_3\n@@ -509,14 +509,14 @@ SYM(__udivsi3):\n #ifndef __ARC_EA__\n SYM(__divsi3):\n \t/* A5 / ARC60? */\n-\tmov r7,blink\n-\txor r6,r0,r1\n+\tmov r12,blink\n+\txor r11,r0,r1\n \tabs_s r0,r0\n \tbl.d @SYM(__udivmodsi4)\n-\t abs_s r1,r1\n-\ttst r6,r6\n-\tj.d [r7]\n-\t neg.mi r0,r0\n+\tabs_s r1,r1\n+\ttst r11,r11\n+\tj.d [r12]\n+\tneg.mi r0,r0\n #else \t/* !ifndef __ARC_EA__ */\n \t;; We can use the abs, norm, divaw and mpy instructions for ARC700\n #define MULDIV\n@@ -913,14 +913,14 @@ SYM(__modsi3):\n #ifndef __ARC_EA__\n \t/* A5 / ARC60? */\n \tmov_s r12,blink\n-\tmov_s r6,r0\n+\tmov_s r11,r0\n \tabs_s r0,r0\n \tbl.d @SYM(__udivmodsi4)\n-\t abs_s r1,r1\n-\ttst r6,r6\n+\tabs_s r1,r1\n+\ttst r11,r11\n \tneg_s r0,r1\n \tj_s.d [r12]\n-\t mov.pl r0,r1\n+\tmov.pl r0,r1\n #else /* __ARC_EA__ */\n \tabs_s\tr2,r1\n \tnorm.f\tr4,r0\n","prefixes":["3/6","ARC"]}