{"id":833311,"url":"http://patchwork.ozlabs.org/api/1.2/patches/833311/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1509622400-13351-1-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509622400-13351-1-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-11-02T11:33:20","name":"[v2] translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"93bb09d05e5984428075d82a6f3baad363d5f9ee","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.2/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1509622400-13351-1-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":11486,"url":"http://patchwork.ozlabs.org/api/1.2/series/11486/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=11486","date":"2017-11-02T11:33:20","name":"[v2] translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD","version":2,"mbox":"http://patchwork.ozlabs.org/series/11486/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/833311/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/833311/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ySNJK42j0z9t2M\n\tfor ;\n\tThu, 2 Nov 2017 22:33:37 +1100 (AEDT)","from localhost ([::1]:59736 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1eADkd-00070d-Le\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Nov 2017 07:33:35 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43578)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1eADk8-0006zj-OC\n\tfor qemu-devel@nongnu.org; Thu, 02 Nov 2017 07:33:07 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1eADk7-0007Ur-Jg\n\tfor qemu-devel@nongnu.org; Thu, 02 Nov 2017 07:33:04 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:38112)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1eADk4-0007Pu-IY; Thu, 02 Nov 2017 07:33:00 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1eADjw-0002cf-1u; Thu, 02 Nov 2017 11:32:52 +0000"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Thu, 2 Nov 2017 11:33:20 +0000","Message-Id":"<1509622400-13351-1-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH v2] translate.c: Fix usermode big-endian\n\tAArch32 LDREXD and STREXD","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"christophe.lyon@linaro.org, Richard Henderson ,\n\tpatches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"For AArch32 LDREXD and STREXD, architecturally the 32-bit word at the\nlowest address is always Rt and the one at addr+4 is Rt2, even if the\nCPU is big-endian. Our implementation does these with a single\n64-bit store, so if we're big-endian then we need to put the two\n32-bit halves together in the opposite order to little-endian,\nso that they end up in the right places. We were trying to do\nthis with the gen_aa32_frob64() function, but that is not correct\nfor the usermode emulator, because there there is a distinction\nbetween \"load a 64 bit value\" (which does a BE 64-bit access\nand doesn't need swapping) and \"load two 32 bit values as one\n64 bit access\" (where we still need to do the swapping, like\nsystem mode BE32).\n\nFixes: https://bugs.launchpad.net/qemu/+bug/1725267\nCc: qemu-stable@nongnu.org\nSigned-off-by: Peter Maydell \n---\nChanges v1->v2:\n * use correct \"s->be_data == MO_BE\" check for bigendian\n * don't mangle the data from the atomic-cmpxchg before\n comparing against expected value\n * tcg_temp_free() the TCGv from gen_aa32_addr()\n * name that TCGv \"taddr\" rather than \"a\"...\n\n target/arm/translate.c | 39 ++++++++++++++++++++++++++++++++++-----\n 1 file changed, 34 insertions(+), 5 deletions(-)","diff":"diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 6ba4ae9..0ed03d7 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -7903,9 +7903,27 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,\n TCGv_i32 tmp2 = tcg_temp_new_i32();\n TCGv_i64 t64 = tcg_temp_new_i64();\n \n- gen_aa32_ld_i64(s, t64, addr, get_mem_index(s), opc);\n+ /* For AArch32, architecturally the 32-bit word at the lowest\n+ * address is always Rt and the one at addr+4 is Rt2, even if\n+ * the CPU is big-endian. That means we don't want to do a\n+ * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if\n+ * for an architecturally 64-bit access, but instead do a\n+ * 64-bit access using MO_BE if appropriate and then split\n+ * the two halves.\n+ * This only makes a difference for BE32 user-mode, where\n+ * frob64() must not flip the two halves of the 64-bit data\n+ * but this code must treat BE32 user-mode like BE32 system.\n+ */\n+ TCGv taddr = gen_aa32_addr(s, addr, opc);\n+\n+ tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc);\n+ tcg_temp_free(taddr);\n tcg_gen_mov_i64(cpu_exclusive_val, t64);\n- tcg_gen_extr_i64_i32(tmp, tmp2, t64);\n+ if (s->be_data == MO_BE) {\n+ tcg_gen_extr_i64_i32(tmp2, tmp, t64);\n+ } else {\n+ tcg_gen_extr_i64_i32(tmp, tmp2, t64);\n+ }\n tcg_temp_free_i64(t64);\n \n store_reg(s, rt2, tmp2);\n@@ -7954,15 +7972,26 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n TCGv_i64 n64 = tcg_temp_new_i64();\n \n t2 = load_reg(s, rt2);\n- tcg_gen_concat_i32_i64(n64, t1, t2);\n+ /* For AArch32, architecturally the 32-bit word at the lowest\n+ * address is always Rt and the one at addr+4 is Rt2, even if\n+ * the CPU is big-endian. Since we're going to treat this as a\n+ * single 64-bit BE store, we need to put the two halves in the\n+ * opposite order for BE to LE, so that they end up in the right\n+ * places.\n+ * We don't want gen_aa32_frob64() because that does the wrong\n+ * thing for BE32 usermode.\n+ */\n+ if (s->be_data == MO_BE) {\n+ tcg_gen_concat_i32_i64(n64, t2, t1);\n+ } else {\n+ tcg_gen_concat_i32_i64(n64, t1, t2);\n+ }\n tcg_temp_free_i32(t2);\n- gen_aa32_frob64(s, n64);\n \n tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64,\n get_mem_index(s), opc);\n tcg_temp_free_i64(n64);\n \n- gen_aa32_frob64(s, o64);\n tcg_gen_setcond_i64(TCG_COND_NE, o64, o64, cpu_exclusive_val);\n tcg_gen_extrl_i64_i32(t0, o64);\n \n","prefixes":["v2"]}