{"id":833266,"url":"http://patchwork.ozlabs.org/api/1.2/patches/833266/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20171102093625.32342-1-ppandit@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171102093625.32342-1-ppandit@redhat.com>","list_archive_url":null,"date":"2017-11-02T09:36:25","name":"pc: restrict port92 register value to 2 bits","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"35c5867ba9ddd7536a1850a2b876d982af76eaaf","submitter":{"id":67408,"url":"http://patchwork.ozlabs.org/api/1.2/people/67408/?format=json","name":"Prasad Pandit","email":"ppandit@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20171102093625.32342-1-ppandit@redhat.com/mbox/","series":[{"id":11460,"url":"http://patchwork.ozlabs.org/api/1.2/series/11460/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=11460","date":"2017-11-02T09:36:25","name":"pc: restrict port92 register value to 2 bits","version":1,"mbox":"http://patchwork.ozlabs.org/series/11460/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/833266/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/833266/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ppandit@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ySKk30Lqxz9s7c\n\tfor ;\n\tThu, 2 Nov 2017 20:37:13 +1100 (AEDT)","from localhost ([::1]:59366 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1eABvw-0007PU-W1\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Nov 2017 05:37:09 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:57185)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1eABvS-0007Nx-PR\n\tfor qemu-devel@nongnu.org; Thu, 02 Nov 2017 05:36:39 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1eABvP-000490-M7\n\tfor qemu-devel@nongnu.org; Thu, 02 Nov 2017 05:36:38 -0400","from mx1.redhat.com ([209.132.183.28]:33892)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1eABvP-00047K-FU\n\tfor qemu-devel@nongnu.org; Thu, 02 Nov 2017 05:36:35 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 7B96580C1A;\n\tThu, 2 Nov 2017 09:36:33 +0000 (UTC)","from localhost.localdomain (unknown [10.35.206.17])\n\tby smtp.corp.redhat.com (Postfix) with ESMTPS id C23D15C54E;\n\tThu, 2 Nov 2017 09:36:30 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 7B96580C1A","From":"P J P ","To":"Qemu Developers ","Date":"Thu, 2 Nov 2017 15:06:25 +0530","Message-Id":"<20171102093625.32342-1-ppandit@redhat.com>","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.26]);\n\tThu, 02 Nov 2017 09:36:33 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH] pc: restrict port92 register value to 2 bits","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Paolo Bonzini ,\n\tPrasad J Pandit ,\n\tNiu Guoxiang ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Prasad J Pandit \n\nPort 92 configuration register holds an 8-bit value. Of 8-bits,\nbits 0-1 are used and 2-7 are reserved. Restrict the supplied\nvalue to 2 bits.\n\nReported-by: Niu Guoxiang \nSigned-off-by: Prasad J Pandit \n---\n hw/i386/pc.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/hw/i386/pc.c b/hw/i386/pc.c\nindex 05985d4927..883384a599 100644\n--- a/hw/i386/pc.c\n+++ b/hw/i386/pc.c\n@@ -515,6 +515,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,\n Port92State *s = opaque;\n int oldval = s->outport;\n \n+ val &= 0x03;\n DPRINTF(\"port92: write 0x%02\" PRIx64 \"\\n\", val);\n s->outport = val;\n qemu_set_irq(s->a20_out, (val >> 1) & 1);\n","prefixes":[]}