{"id":833150,"url":"http://patchwork.ozlabs.org/api/1.2/patches/833150/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20171102003606.19913-5-david.daney@cavium.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/1.2/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171102003606.19913-5-david.daney@cavium.com>","list_archive_url":null,"date":"2017-11-02T00:36:03","name":"[4/7] MIPS: Octeon: Add Free Pointer Unit (FPA) support.","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"802c34e75901b452673ccf7f89b41cb5da11b2ab","submitter":{"id":8400,"url":"http://patchwork.ozlabs.org/api/1.2/people/8400/?format=json","name":"David Daney","email":"david.daney@cavium.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/1.2/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20171102003606.19913-5-david.daney@cavium.com/mbox/","series":[{"id":11414,"url":"http://patchwork.ozlabs.org/api/1.2/series/11414/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=11414","date":"2017-11-02T00:35:59","name":"Cavium OCTEON-III network driver.","version":1,"mbox":"http://patchwork.ozlabs.org/series/11414/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/833150/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/833150/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"ZPBXfh69\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=David.Daney@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yS5mJ6qtJz9t2l\n\tfor ;\n\tThu, 2 Nov 2017 11:38:24 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934016AbdKBAiK (ORCPT );\n\tWed, 1 Nov 2017 20:38:10 -0400","from mail-sn1nam02on0046.outbound.protection.outlook.com\n\t([104.47.36.46]:43314\n\t\"EHLO NAM02-SN1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S933093AbdKBAgo (ORCPT );\n\tWed, 1 Nov 2017 20:36:44 -0400","from ddl.caveonetworks.com (50.233.148.156) by\n\tCY4PR07MB3496.namprd07.prod.outlook.com (10.171.252.153) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.178.6; Thu, 2 Nov 2017 00:36:36 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=Ppa3RHk6GaWC96XywCXu84rWxnEGPHIK640uMd5r5+E=;\n\tb=ZPBXfh69wtog0ISM7Udgx3KGM9W4SQW2Uuyyvn2ApwE1GfFkJiaU6DHliTe7q3KLkM7ji0y1PsnBNHu+zE0MbucWSSi7qCEN0i2AqEZAmGX5hYlEZC7wMX0QXyiTS+G1zkBAjzmnJoZTOfE7OH+7W6Tas9+3VHuXOx9utnTq6j0=","From":"David Daney ","To":"linux-mips@linux-mips.org, ralf@linux-mips.org,\n\tJames Hogan , netdev@vger.kernel.org,\n\t\"David S. Miller\" ,\n\tRob Herring , Mark Rutland ","Cc":"linux-kernel@vger.kernel.org, \"Steven J. Hill\" ,\n\tdevicetree@vger.kernel.org, Carlos Munoz ,\n\t\"Steven J . Hill\" ,\n\tDavid Daney ","Subject":"[PATCH 4/7] MIPS: Octeon: Add Free Pointer Unit (FPA) support.","Date":"Wed, 1 Nov 2017 17:36:03 -0700","Message-Id":"<20171102003606.19913-5-david.daney@cavium.com>","X-Mailer":"git-send-email 2.13.6","In-Reply-To":"<20171102003606.19913-1-david.daney@cavium.com>","References":"<20171102003606.19913-1-david.daney@cavium.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[50.233.148.156]","X-ClientProxiedBy":"CO2PR07CA0072.namprd07.prod.outlook.com (10.174.192.40) To\n\tCY4PR07MB3496.namprd07.prod.outlook.com (10.171.252.153)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"1c21cc34-4e56-4262-b3b8-08d52189c9f8","X-Microsoft-Antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(22001)(4534020)(4602075)(2017052603199);\n\tSRVR:CY4PR07MB3496; ","X-Microsoft-Exchange-Diagnostics":["1; CY4PR07MB3496;\n\t3:tCNfsVrDzqKiYKM9CVJATzKGX3VBFUK1Nb1afb1tNtmMWW2eNJd4pnDStXoFoZt085cKRxhXwnXAgGsfz45gvhEFhj6zxZsLCh8jAHSarP7aSls52fHsXIALKdqoOeqPJUaYAUnGk34zk2dSF/sD81f+Yt1Hq2zdREMiL7xCmkavauAMkZqmIQYlF/RMIQRIC06kg3u0PTu1mbUQ3etPKg3DGdtUnpWny1UHnYv1u+yY74Qb3RP/0GxfyCcNRoxf;\n\t25:CDsBcQLQa7Uowd1gwUDnXWtsL0uC/Az5L0rooomqj5YyAI94pk8kjxvRUM+WSgQVXwvJgQg8KRrRgqzXXj6GLzKiJbqP4EkyYZ6hhsuE5Y59Iz/G3SQlPLeY4bXJsw44LcvZg6CgQmpSjLlK0uHxEmchHqguh7APxD7OTb22g/dEqN2JvQ0gEmZ5oelozIMuh3nWdkwCfAqNKbWDSJ+VhqGUnzBEzQMjm6WQ+dww/J6DrowLv+FmVpjjPJdrMAxHi3sFM6jQwhi4909FGpicc6wFKFSn97nQovRF4gstAUTG9+J3xvnG3IdeM8R6qtWCWhn/ypx4qFRPCE29Wt6Reg==;\n\t31:EmD241meJGrAIqhgfx+kx1ixhEa+v/gqAZpXAPg4AOlB3qviidpwbr2N36iO2BuktIpQ8du7TVM0bwUol/5tbp2I80j6dgULxU7LssMcCw8sPm5icO1I3Y/ofG0ZMKFAHFaJxxflm9BKKZ/PT8AqywIuAss/wYiOC93D6sfN7AiaHUzg+WHrLTCu4UH0bsCEN16igQkqczpqSVeb4cVCRySBvUBttfBMh0/ThWquOVk=","1; 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(10201501046)(93006095)(93001095)(3002001)(100000703101)(100105400095)(3231020)(6041248)(20161123555025)(20161123560025)(20161123562025)(20161123564025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY4PR07MB3496; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY4PR07MB3496; ","X-Forefront-PRVS":"047999FF16","X-Forefront-Antispam-Report":"SFV:NSPM;\n\tSFS:(10009020)(6009001)(346002)(376002)(189002)(199003)(25786009)(72206003)(16526018)(50226002)(53416004)(7736002)(105586002)(305945005)(101416001)(48376002)(478600001)(50986999)(6506006)(76176999)(50466002)(33646002)(47776003)(5003940100001)(106356001)(107886003)(68736007)(2906002)(4326008)(6666003)(6486002)(2950100002)(6512007)(316002)(110136005)(97736004)(16586007)(54906003)(5660300001)(53936002)(189998001)(3846002)(36756003)(6116002)(8936002)(66066001)(1076002)(8676002)(575784001)(81166006)(81156014)(86362001)(69596002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR07MB3496;\n\tH:ddl.caveonetworks.com; FPR:; SPF:None; PTR:InfoNoRecords;\n\tMX:1; A:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"cavium.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"02 Nov 2017 00:36:36.6013\n\t(UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"1c21cc34-4e56-4262-b3b8-08d52189c9f8","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY4PR07MB3496","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"From: Carlos Munoz \n\nFrom the hardware user manual: \"The FPA is a unit that maintains\npools of pointers to free L2/DRAM memory. To provide QoS, the pools\nare referenced indirectly through 1024 auras. Both core software\nand hardware units allocate and free pointers.\"\n\nSigned-off-by: Carlos Munoz \nSigned-off-by: Steven J. Hill \nSigned-off-by: David Daney \n---\n arch/mips/cavium-octeon/Kconfig | 10 +\n arch/mips/cavium-octeon/Makefile | 1 +\n arch/mips/cavium-octeon/octeon-fpa3.c | 363 ++++++++++++++++++++++++++++++++++\n arch/mips/include/asm/octeon/octeon.h | 15 ++\n 4 files changed, 389 insertions(+)\n create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c","diff":"diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig\nindex 5c0b56203bae..211ef5b57214 100644\n--- a/arch/mips/cavium-octeon/Kconfig\n+++ b/arch/mips/cavium-octeon/Kconfig\n@@ -86,4 +86,14 @@ config OCTEON_ILM\n \t To compile this driver as a module, choose M here. The module\n \t will be called octeon-ilm\n \n+config OCTEON_FPA3\n+\ttristate \"Octeon III fpa driver\"\n+\tdefault \"n\"\n+\tdepends on CPU_CAVIUM_OCTEON\n+\thelp\n+\t This option enables a Octeon III driver for the Free Pool Unit (FPA).\n+\t The FPA is a hardware unit that manages pools of pointers to free\n+\t L2/DRAM memory. This driver provides an interface to reserve,\n+\t initialize, and fill fpa pools.\n+\n endif # CAVIUM_OCTEON_SOC\ndiff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile\nindex 0a299ab8719f..0ef967399702 100644\n--- a/arch/mips/cavium-octeon/Makefile\n+++ b/arch/mips/cavium-octeon/Makefile\n@@ -20,3 +20,4 @@ obj-$(CONFIG_MTD)\t\t += flash_setup.o\n obj-$(CONFIG_SMP)\t\t += smp.o\n obj-$(CONFIG_OCTEON_ILM)\t += oct_ilm.o\n obj-$(CONFIG_USB)\t\t += octeon-usb.o\n+obj-$(CONFIG_OCTEON_FPA3)\t += octeon-fpa3.o\ndiff --git a/arch/mips/cavium-octeon/octeon-fpa3.c b/arch/mips/cavium-octeon/octeon-fpa3.c\nnew file mode 100644\nindex 000000000000..65e8081b6a3b\n--- /dev/null\n+++ b/arch/mips/cavium-octeon/octeon-fpa3.c\n@@ -0,0 +1,363 @@\n+/*\n+ * Driver for the Octeon III Free Pool Unit (fpa).\n+ *\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License. See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2015-2017 Cavium, Inc.\n+ */\n+\n+#include \n+\n+#include \n+\n+\n+/* Registers are accessed via xkphys */\n+#define SET_XKPHYS\t\t\t(1ull << 63)\n+#define NODE_OFFSET\t\t\t0x1000000000ull\n+#define SET_NODE(node)\t\t\t((node) * NODE_OFFSET)\n+\n+#define FPA_BASE\t\t\t0x1280000000000ull\n+#define SET_FPA_BASE(node)\t\t(SET_XKPHYS + SET_NODE(node) + FPA_BASE)\n+\n+#define FPA_GEN_CFG(n)\t\t\t(SET_FPA_BASE(n) + 0x00000050)\n+\n+#define FPA_POOLX_CFG(n, p)\t\t(SET_FPA_BASE(n) + (p<<3) + 0x10000000)\n+#define FPA_POOLX_START_ADDR(n, p)\t(SET_FPA_BASE(n) + (p<<3) + 0x10500000)\n+#define FPA_POOLX_END_ADDR(n, p)\t(SET_FPA_BASE(n) + (p<<3) + 0x10600000)\n+#define FPA_POOLX_STACK_BASE(n, p)\t(SET_FPA_BASE(n) + (p<<3) + 0x10700000)\n+#define FPA_POOLX_STACK_END(n, p)\t(SET_FPA_BASE(n) + (p<<3) + 0x10800000)\n+#define FPA_POOLX_STACK_ADDR(n, p)\t(SET_FPA_BASE(n) + (p<<3) + 0x10900000)\n+\n+#define FPA_AURAX_POOL(n, a)\t\t(SET_FPA_BASE(n) + (a<<3) + 0x20000000)\n+#define FPA_AURAX_CFG(n, a)\t\t(SET_FPA_BASE(n) + (a<<3) + 0x20100000)\n+#define FPA_AURAX_CNT(n, a)\t\t(SET_FPA_BASE(n) + (a<<3) + 0x20200000)\n+#define FPA_AURAX_CNT_LIMIT(n, a)\t(SET_FPA_BASE(n) + (a<<3) + 0x20400000)\n+#define FPA_AURAX_CNT_THRESHOLD(n, a)\t(SET_FPA_BASE(n) + (a<<3) + 0x20500000)\n+#define FPA_AURAX_POOL_LEVELS(n, a)\t(SET_FPA_BASE(n) + (a<<3) + 0x20700000)\n+#define FPA_AURAX_CNT_LEVELS(n, a)\t(SET_FPA_BASE(n) + (a<<3) + 0x20800000)\n+\n+static inline u64 oct_csr_read(u64 addr)\n+{\n+\treturn __raw_readq((void __iomem *)addr);\n+}\n+\n+static inline void oct_csr_write(u64 data, u64 addr)\n+{\n+\t__raw_writeq(data, (void __iomem *)addr);\n+}\n+\n+static DEFINE_MUTEX(octeon_fpa3_lock);\n+\n+static int get_num_pools(void)\n+{\n+\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\treturn 64;\n+\tif (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))\n+\t\treturn 32;\n+\treturn 0;\n+}\n+\n+static int get_num_auras(void)\n+{\n+\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\treturn 1024;\n+\tif (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))\n+\t\treturn 512;\n+\treturn 0;\n+}\n+\n+/**\n+ * octeon_fpa3_init - Initialize the fpa to default values.\n+ * @node: Node of fpa to initialize.\n+ *\n+ * Returns 0 if successful.\n+ * Returns <0 for error codes.\n+ */\n+int octeon_fpa3_init(int node)\n+{\n+\tstatic bool init_done[2];\n+\tu64 data;\n+\tint aura_cnt, i;\n+\n+\tmutex_lock(&octeon_fpa3_lock);\n+\n+\tif (init_done[node])\n+\t\tgoto done;\n+\n+\taura_cnt = get_num_auras();\n+\tfor (i = 0; i < aura_cnt; i++) {\n+\t\toct_csr_write(0x100000000ull, FPA_AURAX_CNT(node, i));\n+\t\toct_csr_write(0xfffffffffull, FPA_AURAX_CNT_LIMIT(node, i));\n+\t\toct_csr_write(0xffffffffeull, FPA_AURAX_CNT_THRESHOLD(node, i));\n+\t}\n+\n+\tdata = oct_csr_read(FPA_GEN_CFG(node));\n+\tdata &= ~GENMASK_ULL(9, 4);\n+\tdata |= 3 << 4;\n+\toct_csr_write(data, FPA_GEN_CFG(node));\n+\n+\tinit_done[node] = 1;\n+ done:\n+\tmutex_unlock(&octeon_fpa3_lock);\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(octeon_fpa3_init);\n+\n+/**\n+ * octeon_fpa3_pool_init - Initialize a pool.\n+ * @node: Node to initialize pool on.\n+ * @pool_num: Requested pool number (-1 for don't care).\n+ * @pool: Updated with the initialized pool number.\n+ * @pool_stack: Updated with the base of the memory allocated for the pool\n+ *\t\tstack.\n+ * @num_ptrs: Number of pointers to allocated on the stack.\n+ *\n+ * Returns 0 if successful.\n+ * Returns <0 for error codes.\n+ */\n+int octeon_fpa3_pool_init(int node, int pool_num, int *pool, void **pool_stack, int num_ptrs)\n+{\n+\tstruct global_resource_tag tag;\n+\tchar buf[16];\n+\tu64 pool_stack_start, pool_stack_end, data;\n+\tint stack_size, rc = 0;\n+\n+\tmutex_lock(&octeon_fpa3_lock);\n+\n+\tstrncpy((char *)&tag.lo, \"cvm_pool\", 8);\n+\tsnprintf(buf, 16, \"_%d......\", node);\n+\tmemcpy(&tag.hi, buf, 8);\n+\n+\tres_mgr_create_resource(tag, get_num_pools());\n+\t*pool = res_mgr_alloc(tag, pool_num, true);\n+\tif (*pool < 0) {\n+\t\trc = -ENODEV;\n+\t\tgoto error;\n+\t}\n+\n+\toct_csr_write(0, FPA_POOLX_CFG(node, *pool));\n+\toct_csr_write(128, FPA_POOLX_START_ADDR(node, *pool));\n+\toct_csr_write(GENMASK_ULL(41, 7), FPA_POOLX_END_ADDR(node, *pool));\n+\n+\tstack_size = (DIV_ROUND_UP(num_ptrs, 29) + 1) * 128;\n+\t*pool_stack = kmalloc_node(stack_size, GFP_KERNEL, node);\n+\tif (!*pool_stack) {\n+\t\tpr_err(\"Failed to allocate pool stack memory pool=%d\\n\",\n+\t\t pool_num);\n+\t\trc = -ENOMEM;\n+\t\tgoto error_stack;\n+\t}\n+\n+\tpool_stack_start = virt_to_phys(*pool_stack);\n+\tpool_stack_end = round_down(pool_stack_start + stack_size, 128);\n+\tpool_stack_start = round_up(pool_stack_start, 128);\n+\toct_csr_write(pool_stack_start, FPA_POOLX_STACK_BASE(node, *pool));\n+\toct_csr_write(pool_stack_start, FPA_POOLX_STACK_ADDR(node, *pool));\n+\toct_csr_write(pool_stack_end, FPA_POOLX_STACK_END(node, *pool));\n+\n+\tdata = (2 << 3) | BIT(0);\n+\toct_csr_write(data, FPA_POOLX_CFG(node, *pool));\n+\n+\tmutex_unlock(&octeon_fpa3_lock);\n+\treturn 0;\n+\n+error_stack:\n+\tres_mgr_free(tag, *pool);\n+error:\n+\tmutex_unlock(&octeon_fpa3_lock);\n+\treturn rc;\n+}\n+EXPORT_SYMBOL(octeon_fpa3_pool_init);\n+\n+/**\n+ * octeon_fpa3_release_pool - Release a pool.\n+ * @node: Node pool is on.\n+ * @pool: Pool to release.\n+ */\n+void octeon_fpa3_release_pool(int node, int pool)\n+{\n+\tstruct global_resource_tag tag;\n+\tchar buf[16];\n+\n+\tmutex_lock(&octeon_fpa3_lock);\n+\n+\tstrncpy((char *)&tag.lo, \"cvm_pool\", 8);\n+\tsnprintf(buf, 16, \"_%d......\", node);\n+\tmemcpy(&tag.hi, buf, 8);\n+\n+\tres_mgr_free(tag, pool);\n+\n+\tmutex_unlock(&octeon_fpa3_lock);\n+}\n+EXPORT_SYMBOL(octeon_fpa3_release_pool);\n+\n+/**\n+ * octeon_fpa3_aura_init - Initialize an aura.\n+ * @node: Node to initialize aura on.\n+ * @pool: Pool the aura belongs to.\n+ * @aura_num: Requested aura number (-1 for don't care).\n+ * @aura: Updated with the initialized aura number.\n+ * @num_bufs: Number of buffers in the aura.\n+ * @limit: Limit for the aura.\n+ *\n+ * Returns 0 if successful.\n+ * Returns <0 for error codes.\n+ */\n+int octeon_fpa3_aura_init(int node, int pool, int aura_num, int *aura, int num_bufs, unsigned int limit)\n+{\n+\tstruct global_resource_tag tag;\n+\tchar buf[16];\n+\tu64 data, shift;\n+\tunsigned int drop, pass;\n+\tint rc = 0;\n+\n+\tmutex_lock(&octeon_fpa3_lock);\n+\n+\tstrncpy((char *)&tag.lo, \"cvm_aura\", 8);\n+\tsnprintf(buf, 16, \"_%d......\", node);\n+\tmemcpy(&tag.hi, buf, 8);\n+\n+\tres_mgr_create_resource(tag, get_num_auras());\n+\t*aura = res_mgr_alloc(tag, aura_num, true);\n+\tif (*aura < 0) {\n+\t\trc = -ENODEV;\n+\t\tgoto error;\n+\t}\n+\n+\toct_csr_write(0, FPA_AURAX_CFG(node, *aura));\n+\n+\t/* Allow twice the limit before saturation at zero */\n+\tlimit *= 2;\n+\tdata = limit;\n+\toct_csr_write(data, FPA_AURAX_CNT_LIMIT(node, *aura));\n+\toct_csr_write(data, FPA_AURAX_CNT(node, *aura));\n+\n+\toct_csr_write(pool, FPA_AURAX_POOL(node, *aura));\n+\n+\t/* No per-pool RED/Drop */\n+\toct_csr_write(0, FPA_AURAX_POOL_LEVELS(node, *aura));\n+\n+\tshift = 0;\n+\twhile ((limit >> shift) > 255)\n+\t\tshift++;\n+\n+\tdrop = (limit - num_bufs / 20) >> shift;\t/* 95% */\n+\tpass = (limit - (num_bufs * 3) / 20) >> shift;\t/* 85% */\n+\n+\t/* Enable per aura RED/drop */\n+\tdata = BIT(38) | (shift << 32) | (drop << 16) | (pass << 8);\n+\toct_csr_write(data, FPA_AURAX_CNT_LEVELS(node, *aura));\n+\n+error:\n+\tmutex_unlock(&octeon_fpa3_lock);\n+\treturn rc;\n+}\n+EXPORT_SYMBOL(octeon_fpa3_aura_init);\n+\n+/**\n+ * octeon_fpa3_release_aura - Release an aura.\n+ * @node: Node to aura is on.\n+ * @aura: Aura to release.\n+ */\n+void octeon_fpa3_release_aura(int node, int aura)\n+{\n+\tstruct global_resource_tag tag;\n+\tchar buf[16];\n+\n+\tmutex_lock(&octeon_fpa3_lock);\n+\n+\tstrncpy((char *)&tag.lo, \"cvm_aura\", 8);\n+\tsnprintf(buf, 16, \"_%d......\", node);\n+\tmemcpy(&tag.hi, buf, 8);\n+\n+\tres_mgr_free(tag, aura);\n+\n+\tmutex_unlock(&octeon_fpa3_lock);\n+}\n+EXPORT_SYMBOL(octeon_fpa3_release_aura);\n+\n+/**\n+ * octeon_fpa3_alloc - Get a buffer from a aura's pool.\n+ * @node: Node to free memory to.\n+ * @aura: Aura to free memory to.\n+ *\n+ * Returns allocated buffer pointer if successful\n+ * Returns NULL on error.\n+ */\n+void *octeon_fpa3_alloc(u64 node, int aura)\n+{\n+\tu64 buf_phys, addr;\n+\tvoid *buf = NULL;\n+\n+\t/* Buffer pointers are obtained using load operations */\n+\taddr = BIT(63) | BIT(48) | (0x29ull << 40) | (node << 36) |\n+\t\t(aura << 16);\n+\tbuf_phys = *(u64 *)addr;\n+\n+\tif (buf_phys)\n+\t\tbuf = phys_to_virt(buf_phys);\n+\n+\treturn buf;\n+}\n+EXPORT_SYMBOL(octeon_fpa3_alloc);\n+\n+/**\n+ * octeon_fpa3_free - Add a buffer back to the aura's pool.\n+ * @node: Node to free memory to.\n+ * @aura: Aura to free memory to.\n+ * @buf: Address of buffer to free to the aura's pool.\n+ */\n+void octeon_fpa3_free(u64 node, int aura, const void *buf)\n+{\n+\tu64 buf_phys, addr;\n+\n+\tbuf_phys = virt_to_phys(buf);\n+\n+\t/* Make sure that any previous writes to memory go out before we free\n+\t * this buffer. This also serves as a barrier to prevent GCC from\n+\t * reordering operations to after the free.\n+\t */\n+\twmb();\n+\n+\t/* Buffers are added to fpa pools using store operations */\n+\taddr = BIT(63) | BIT(48) | (0x29ull << 40) | (node << 36) | (aura << 16);\n+\t*(u64 *)addr = buf_phys;\n+}\n+EXPORT_SYMBOL(octeon_fpa3_free);\n+\n+/**\n+ * octeon_fpa3_mem_fill - Add buffers to an aura.\n+ * @node: Node to get memory from.\n+ * @cache: Memory cache to allocate from.\n+ * @aura: Aura to add buffers to.\n+ * @num_bufs: Number of buffers to add to the aura.\n+ *\n+ * Returns 0 if successful.\n+ * Returns <0 for error codes.\n+ */\n+int octeon_fpa3_mem_fill(int node, struct kmem_cache *cache, int aura, int num_bufs)\n+{\n+\tvoid *mem;\n+\tint i, rc = 0;\n+\n+\tmutex_lock(&octeon_fpa3_lock);\n+\n+\tfor (i = 0; i < num_bufs; i++) {\n+\t\tmem = kmem_cache_alloc_node(cache, GFP_KERNEL, node);\n+\t\tif (!mem) {\n+\t\t\tpr_err(\"Failed to allocate memory for aura=%d\\n\", aura);\n+\t\t\trc = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tocteon_fpa3_free(node, aura, mem);\n+\t}\n+\n+\tmutex_unlock(&octeon_fpa3_lock);\n+\treturn rc;\n+}\n+EXPORT_SYMBOL(octeon_fpa3_mem_fill);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"Cavium, Inc. Octeon III FPA manager.\");\ndiff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h\nindex 0411efdb465c..d184592e6515 100644\n--- a/arch/mips/include/asm/octeon/octeon.h\n+++ b/arch/mips/include/asm/octeon/octeon.h\n@@ -10,6 +10,7 @@\n \n #include \n #include \n+#include \n \n extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,\n \t\t\t\t\t\tuint64_t alignment,\n@@ -364,6 +365,20 @@ int res_mgr_alloc_range(struct global_resource_tag tag, int req_inst,\n \t\t\tint req_cnt, bool use_last_avail, int *inst);\n int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt);\n \n+#if IS_ENABLED(CONFIG_OCTEON_FPA3)\n+int octeon_fpa3_init(int node);\n+int octeon_fpa3_pool_init(int node, int pool_num, int *pool, void **pool_stack,\n+\t\t\t int num_ptrs);\n+int octeon_fpa3_aura_init(int node, int pool, int aura_num, int *aura,\n+\t\t\t int num_bufs, unsigned int limit);\n+int octeon_fpa3_mem_fill(int node, struct kmem_cache *cache, int aura,\n+\t\t\t int num_bufs);\n+void octeon_fpa3_free(u64 node, int aura, const void *buf);\n+void *octeon_fpa3_alloc(u64 node, int aura);\n+void octeon_fpa3_release_pool(int node, int pool);\n+void octeon_fpa3_release_aura(int node, int aura);\n+#endif\n+\n /**\n * Read a 32bit value from the Octeon NPI register space\n *\n","prefixes":["4/7"]}