{"id":831248,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831248/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-15-git-send-email-Dave.Martin@arm.com/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/1.2/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509101470-7881-15-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-10-27T10:50:56","name":"[v4,14/28] arm64/sve: Backend logic for setting the vector length","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a43ad88cd976f6930b13ae944dd2257893d1d4d1","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-15-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":10556,"url":"http://patchwork.ozlabs.org/api/1.2/series/10556/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=10556","date":"2017-10-27T10:50:43","name":"ARM Scalable Vector Extension (SVE)","version":4,"mbox":"http://patchwork.ozlabs.org/series/10556/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831248/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831248/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"iyGewsWV\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNgx51RLvz9sNx\n\tfor ;\n\tFri, 27 Oct 2017 22:04:09 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e82Qj-0007XH-Fu; Fri, 27 Oct 2017 11:04:01 +0000","from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e82FA-0003x7-QF for linux-arm-kernel@lists.infradead.org;\n\tFri, 27 Oct 2017 10:52:22 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A88415BE;\n\tFri, 27 Oct 2017 03:51:47 -0700 (PDT)","from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t4FCDA3F24A; Fri, 27 Oct 2017 03:51:45 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=tea53RYVtelui8+53WjswUVZz26tNxo7tF+dUbz7sAk=;\n\tb=iyGewsWVjOwXXH\n\tFpM2/dtqAZZiKp62ZRaxrOLHAHNvFvUBisQQ/+r9pk/GIK69OTOFgKFdW1eixhygzVM2hY9anhFOZ\n\tflJahOPlqaDm6h8Qmf9wkF9Ie5eljAAH7NkEwgyUCiFSiq1ExGqiBbeIN8wv7Isnt+93Y+VI/6h3e\n\tVHOwDidwdiofq9Cdq4RMjH/G0MfkgLXPSpw8iKr8iMz7fIoTWsWMQemUDQbvrPbZ+xGduiKnQ5L2r\n\tRKHMDYlq4mpnLNVrmebXJbYB1BiBho9SX18OE+fKLy08YRtjxKHIuiq77fwB5llC4n0FfVUB4r+6+\n\tzZITqfMeuSklGzjuLAFQ==;","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Subject":"[PATCH v4 14/28] arm64/sve: Backend logic for setting the vector\n\tlength","Date":"Fri, 27 Oct 2017 11:50:56 +0100","Message-Id":"<1509101470-7881-15-git-send-email-Dave.Martin@arm.com>","X-Mailer":"git-send-email 2.1.4","In-Reply-To":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171027_035205_695009_4AF57BFF ","X-CRM114-Status":"GOOD ( 24.32 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, Okamoto Takayuki ,\n\tlibc-alpha@sourceware.org, Ard Biesheuvel , \n\tSzabolcs Nagy , \n\tCatalin Marinas ,\n\tWill Deacon , =?utf-8?q?Alex_Benn=C3=A9e?=\n\t, kvmarm@lists.cs.columbia.edu","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"This patch implements the core logic for changing a task's vector\nlength on request from userspace. This will be used by the ptrace\nand prctl frontends that are implemented in later patches.\n\nThe SVE architecture permits, but does not require, implementations\nto support vector lengths that are not a power of two. To handle\nthis, logic is added to check a requested vector length against a\npossibly sparse bitmap of available vector lengths at runtime, so\nthat the best supported value can be chosen.\n\nSigned-off-by: Dave Martin \nReviewed-by: Catalin Marinas \nCc: Alex Bennée \n---\n arch/arm64/include/asm/fpsimd.h | 8 +++\n arch/arm64/kernel/fpsimd.c | 137 +++++++++++++++++++++++++++++++++++++++-\n include/uapi/linux/prctl.h | 5 ++\n 3 files changed, 149 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\nindex 9bbd74c..86f550c 100644\n--- a/arch/arm64/include/asm/fpsimd.h\n+++ b/arch/arm64/include/asm/fpsimd.h\n@@ -20,6 +20,7 @@\n \n #ifndef __ASSEMBLY__\n \n+#include \n #include \n \n /*\n@@ -70,17 +71,24 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state);\n \n extern void fpsimd_flush_task_state(struct task_struct *target);\n \n+/* Maximum VL that SVE VL-agnostic software can transparently support */\n+#define SVE_VL_ARCH_MAX 0x100\n+\n extern void sve_save_state(void *state, u32 *pfpsr);\n extern void sve_load_state(void const *state, u32 const *pfpsr,\n \t\t\t unsigned long vq_minus_1);\n extern unsigned int sve_get_vl(void);\n \n+extern int __ro_after_init sve_max_vl;\n+\n #ifdef CONFIG_ARM64_SVE\n \n extern size_t sve_state_size(struct task_struct const *task);\n \n extern void sve_alloc(struct task_struct *task);\n extern void fpsimd_release_task(struct task_struct *task);\n+extern int sve_set_vector_length(struct task_struct *task,\n+\t\t\t\t unsigned long vl, unsigned long flags);\n \n #else /* ! CONFIG_ARM64_SVE */\n \ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 5063476..476c637 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -17,8 +17,10 @@\n * along with this program. If not, see .\n */\n \n+#include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -27,6 +29,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -112,6 +115,20 @@ static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);\n /* Default VL for tasks that don't set it explicitly: */\n static int sve_default_vl = SVE_VL_MIN;\n \n+#ifdef CONFIG_ARM64_SVE\n+\n+/* Maximum supported vector length across all CPUs (initially poisoned) */\n+int __ro_after_init sve_max_vl = -1;\n+/* Set of available vector lengths, as vq_to_bit(vq): */\n+static DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX);\n+\n+#else /* ! CONFIG_ARM64_SVE */\n+\n+/* Dummy declaration for code that will be optimised out: */\n+extern DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX);\n+\n+#endif /* ! CONFIG_ARM64_SVE */\n+\n /*\n * Call __sve_free() directly only if you know task can't be scheduled\n * or preempted.\n@@ -269,6 +286,50 @@ static void task_fpsimd_save(void)\n \t}\n }\n \n+/*\n+ * Helpers to translate bit indices in sve_vq_map to VQ values (and\n+ * vice versa). This allows find_next_bit() to be used to find the\n+ * _maximum_ VQ not exceeding a certain value.\n+ */\n+\n+static unsigned int vq_to_bit(unsigned int vq)\n+{\n+\treturn SVE_VQ_MAX - vq;\n+}\n+\n+static unsigned int bit_to_vq(unsigned int bit)\n+{\n+\tif (WARN_ON(bit >= SVE_VQ_MAX))\n+\t\tbit = SVE_VQ_MAX - 1;\n+\n+\treturn SVE_VQ_MAX - bit;\n+}\n+\n+/*\n+ * All vector length selection from userspace comes through here.\n+ * We're on a slow path, so some sanity-checks are included.\n+ * If things go wrong there's a bug somewhere, but try to fall back to a\n+ * safe choice.\n+ */\n+static unsigned int find_supported_vector_length(unsigned int vl)\n+{\n+\tint bit;\n+\tint max_vl = sve_max_vl;\n+\n+\tif (WARN_ON(!sve_vl_valid(vl)))\n+\t\tvl = SVE_VL_MIN;\n+\n+\tif (WARN_ON(!sve_vl_valid(max_vl)))\n+\t\tmax_vl = SVE_VL_MIN;\n+\n+\tif (vl > max_vl)\n+\t\tvl = max_vl;\n+\n+\tbit = find_next_bit(sve_vq_map, SVE_VQ_MAX,\n+\t\t\t vq_to_bit(sve_vq_from_vl(vl)));\n+\treturn sve_vl_from_vq(bit_to_vq(bit));\n+}\n+\n #define ZREG(sve_state, vq, n) ((char *)(sve_state) +\t\t\\\n \t(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))\n \n@@ -363,6 +424,76 @@ void sve_alloc(struct task_struct *task)\n \tBUG_ON(!task->thread.sve_state);\n }\n \n+int sve_set_vector_length(struct task_struct *task,\n+\t\t\t unsigned long vl, unsigned long flags)\n+{\n+\tif (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |\n+\t\t\t\t PR_SVE_SET_VL_ONEXEC))\n+\t\treturn -EINVAL;\n+\n+\tif (!sve_vl_valid(vl))\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * Clamp to the maximum vector length that VL-agnostic SVE code can\n+\t * work with. A flag may be assigned in the future to allow setting\n+\t * of larger vector lengths without confusing older software.\n+\t */\n+\tif (vl > SVE_VL_ARCH_MAX)\n+\t\tvl = SVE_VL_ARCH_MAX;\n+\n+\tvl = find_supported_vector_length(vl);\n+\n+\tif (flags & (PR_SVE_VL_INHERIT |\n+\t\t PR_SVE_SET_VL_ONEXEC))\n+\t\ttask->thread.sve_vl_onexec = vl;\n+\telse\n+\t\t/* Reset VL to system default on next exec: */\n+\t\ttask->thread.sve_vl_onexec = 0;\n+\n+\t/* Only actually set the VL if not deferred: */\n+\tif (flags & PR_SVE_SET_VL_ONEXEC)\n+\t\tgoto out;\n+\n+\tif (vl == task->thread.sve_vl)\n+\t\tgoto out;\n+\n+\t/*\n+\t * To ensure the FPSIMD bits of the SVE vector registers are preserved,\n+\t * write any live register state back to task_struct, and convert to a\n+\t * non-SVE thread.\n+\t */\n+\tif (task == current) {\n+\t\tlocal_bh_disable();\n+\n+\t\ttask_fpsimd_save();\n+\t\tset_thread_flag(TIF_FOREIGN_FPSTATE);\n+\t}\n+\n+\tfpsimd_flush_task_state(task);\n+\tif (test_and_clear_tsk_thread_flag(task, TIF_SVE))\n+\t\tsve_to_fpsimd(task);\n+\n+\tif (task == current)\n+\t\tlocal_bh_enable();\n+\n+\t/*\n+\t * Force reallocation of task SVE state to the correct size\n+\t * on next use:\n+\t */\n+\tsve_free(task);\n+\n+\ttask->thread.sve_vl = vl;\n+\n+out:\n+\tif (flags & PR_SVE_VL_INHERIT)\n+\t\tset_tsk_thread_flag(task, TIF_SVE_VL_INHERIT);\n+\telse\n+\t\tclear_tsk_thread_flag(task, TIF_SVE_VL_INHERIT);\n+\n+\treturn 0;\n+}\n+\n /*\n * Called from the put_task_struct() path, which cannot get here\n * unless dead_task is really dead and not schedulable.\n@@ -479,7 +610,7 @@ void fpsimd_thread_switch(struct task_struct *next)\n \n void fpsimd_flush_thread(void)\n {\n-\tint vl;\n+\tint vl, supported_vl;\n \n \tif (!system_supports_fpsimd())\n \t\treturn;\n@@ -507,6 +638,10 @@ void fpsimd_flush_thread(void)\n \t\tif (WARN_ON(!sve_vl_valid(vl)))\n \t\t\tvl = SVE_VL_MIN;\n \n+\t\tsupported_vl = find_supported_vector_length(vl);\n+\t\tif (WARN_ON(supported_vl != vl))\n+\t\t\tvl = supported_vl;\n+\n \t\tcurrent->thread.sve_vl = vl;\n \n \t\t/*\ndiff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h\nindex a8d0759..1b64901 100644\n--- a/include/uapi/linux/prctl.h\n+++ b/include/uapi/linux/prctl.h\n@@ -197,4 +197,9 @@ struct prctl_mm_map {\n # define PR_CAP_AMBIENT_LOWER\t\t3\n # define PR_CAP_AMBIENT_CLEAR_ALL\t4\n \n+/* arm64 Scalable Vector Extension controls */\n+# define PR_SVE_SET_VL_ONEXEC\t\t(1 << 18) /* defer effect until exec */\n+# define PR_SVE_VL_LEN_MASK\t\t0xffff\n+# define PR_SVE_VL_INHERIT\t\t(1 << 17) /* inherit across exec */\n+\n #endif /* _LINUX_PRCTL_H */\n","prefixes":["v4","14/28"]}