{"id":831233,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831233/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-25-git-send-email-Dave.Martin@arm.com/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.2/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509101470-7881-25-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-10-27T10:51:06","name":"[v4,24/28] arm64/sve: KVM: Hide SVE from CPU features exposed to guests","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"61b227a63a14235bcc6fdc4563b97bf3985d2898","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-25-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":10555,"url":"http://patchwork.ozlabs.org/api/1.2/series/10555/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=10555","date":"2017-10-27T10:50:42","name":"ARM Scalable Vector Extension (SVE)","version":4,"mbox":"http://patchwork.ozlabs.org/series/10555/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831233/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831233/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86466-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"R4/IP5vn\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNgll4bR3z9rxj\n\tfor ;\n\tFri, 27 Oct 2017 21:56:03 +1100 (AEDT)","(qmail 121143 invoked by alias); 27 Oct 2017 10:52:09 -0000","(qmail 121103 invoked by uid 89); 27 Oct 2017 10:52:09 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=Iparo9Zy3nIU2YMXfNmHA+nWndj7mxWicjis7FJRwuV\n\tVd/gzabaTkKeRqrlE0vbKlLyzfQ+1UEP3s9Rb3j2S/GcQlwwUzMykrzkdFJqI+Qa\n\tJd8M909FSAE3AVrHs8yyo/qh6okmp/6wVVBIpSI7mFeRpOGpHFbAzGRt0HBU7kC4\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=qkXv1Dnjk+oNPdOdjf8evPNhDjY=; b=R4/IP5vnr3C+SLyVK\n\tS4FDHaXana27eP1Nrufy7qFzgIB0+tmdYFMj+VkTkxfPq5wxb7k/e+AaWFxoeSYL\n\tMdh4pfqGxhET+DyZX+6pbz6MN9vA9XLwDOQrEUXyClU+Iw9HYb4N4CFR/StJ6uy2\n\tY5rGnBOPUKCiqNik+vpT7NskPE=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=believing,\n\tlegitimately","X-HELO":"foss.arm.com","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas , Will Deacon\n\t, \tArd Biesheuvel ,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= ,\n\tSzabolcs Nagy , Okamoto Takayuki\n\t, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v4 24/28] arm64/sve: KVM: Hide SVE from CPU features exposed\n\tto guests","Date":"Fri, 27 Oct 2017 11:51:06 +0100","Message-Id":"<1509101470-7881-25-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"KVM guests cannot currently use SVE, because SVE is always\nconfigured to trap to EL2.\n\nHowever, a guest that sees SVE reported as present in\nID_AA64PFR0_EL1 may legitimately expect that SVE works and try to\nuse it. Instead of working, the guest will receive an injected\nundef exception, which may cause the guest to oops or go into a\nspin.\n\nTo avoid misleading the guest into believing that SVE will work,\nthis patch masks out the SVE field from ID_AA64PFR0_EL1 when a\nguest attempts to read this register. No support is explicitly\nadded for ID_AA64ZFR0_EL1 either, so that is still emulated as\nreading as zero, which is consistent with SVE not being\nimplemented.\n\nThis is a temporary measure, and will be removed in a later series\nwhen full KVM support for SVE is implemented.\n\nSigned-off-by: Dave Martin \nReviewed-by: Alex Bennée \nAcked-by: Marc Zyngier \nAcked-by: Catalin Marinas \nAcked-by: Christoffer Dall \n---\n arch/arm64/kvm/sys_regs.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c\nindex b1f7552..a0ee9b0 100644\n--- a/arch/arm64/kvm/sys_regs.c\n+++ b/arch/arm64/kvm/sys_regs.c\n@@ -23,6 +23,7 @@\n #include \n #include \n #include \n+#include \n #include \n \n #include \n@@ -897,8 +898,17 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)\n {\n \tu32 id = sys_reg((u32)r->Op0, (u32)r->Op1,\n \t\t\t (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);\n+\tu64 val = raz ? 0 : read_sanitised_ftr_reg(id);\n \n-\treturn raz ? 0 : read_sanitised_ftr_reg(id);\n+\tif (id == SYS_ID_AA64PFR0_EL1) {\n+\t\tif (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT))\n+\t\t\tpr_err_once(\"kvm [%i]: SVE unsupported for guests, suppressing\\n\",\n+\t\t\t\t task_pid_nr(current));\n+\n+\t\tval &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);\n+\t}\n+\n+\treturn val;\n }\n \n /* cpufeature ID register access trap handlers */\n","prefixes":["v4","24/28"]}