{"id":831217,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831217/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-14-git-send-email-Dave.Martin@arm.com/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.2/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509101470-7881-14-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-10-27T10:50:55","name":"[v4,13/28] arm64/sve: Signal handling support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b00439e7ba7940d40700f179d9f6b3095e381e97","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-14-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":10555,"url":"http://patchwork.ozlabs.org/api/1.2/series/10555/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=10555","date":"2017-10-27T10:50:42","name":"ARM Scalable Vector Extension (SVE)","version":4,"mbox":"http://patchwork.ozlabs.org/series/10555/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831217/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831217/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86455-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"v2V947By\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNgjQ6Xypz9sNx\n\tfor ;\n\tFri, 27 Oct 2017 21:54:02 +1100 (AEDT)","(qmail 118553 invoked by alias); 27 Oct 2017 10:51:49 -0000","(qmail 118524 invoked by uid 89); 27 Oct 2017 10:51:49 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=C7HH0yWU/IvfnbwIqh5PkFRk6Qo8io4gGL7UUY6DTF0\n\txkF7u4JmZ1wLYfWY+6mGCXzZbnbdiFV4FpxOZFrafdob3qk0oY7q9tbCa7qypMw4\n\tuKJfH0VjWRpPsQUX5XQTUdddekTLonXBZifCbzSBraHaEp+ntPJNTKzxv4SrY03k\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=pBYM0YlhFjjcTzDA+VZqhrRCGxw=; b=v2V947Byfe4MW/jCy\n\tDnyqPxdr6R5GTFJ4EoOluwEuhnc7Saro0k5MrPhv9dhs7CeMyKYVL93Mpmk+CCCG\n\taBIJUShor3lCkPdxp6zRQt0/Li5Y8XjmQCrIk2EGBlogNlWhr3xlYnyGPftWmDx7\n\tTolxsOHgyIJWlPr+wnchdeZoeU=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas , Will Deacon\n\t, \tArd Biesheuvel ,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= ,\n\tSzabolcs Nagy , Okamoto Takayuki\n\t, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v4 13/28] arm64/sve: Signal handling support","Date":"Fri, 27 Oct 2017 11:50:55 +0100","Message-Id":"<1509101470-7881-14-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"This patch implements support for saving and restoring the SVE\nregisters around signals.\n\nA fixed-size header struct sve_context is always included in the\nsignal frame encoding the thread's vector length at the time of\nsignal delivery, optionally followed by a variable-layout structure\nencoding the SVE registers.\n\nBecause of the need to preserve backwards compatibility, the FPSIMD\nview of the SVE registers is always dumped as a struct\nfpsimd_context in the usual way, in addition to any sve_context.\n\nThe SVE vector registers are dumped in full, including bits 127:0\nof each register which alias the corresponding FPSIMD vector\nregisters in the hardware. To avoid any ambiguity about which\nalias to restore during sigreturn, the kernel always restores bits\n127:0 of each SVE vector register from the fpsimd_context in the\nsignal frame (which must be present): userspace needs to take this\ninto account if it wants to modify the SVE vector register contents\non return from a signal.\n\nFPSR and FPCR, which are used by both FPSIMD and SVE, are not\nincluded in sve_context because they are always present in\nfpsimd_context anyway.\n\nFor signal delivery, a new helper\nfpsimd_signal_preserve_current_state() is added to update _both_\nthe FPSIMD and SVE views in the task struct, to make it easier to\npopulate this information into the signal frame. Because of the\nredundancy between the two views of the state, only one is updated\notherwise.\n\nSigned-off-by: Dave Martin \nCc: Alex BennĂ©e \nCc: Ard Biesheuvel \n\n---\n\nChanges since v3\n----------------\n\n**Dropped** Reviewed-by: Catalin Marinas \nThe changes are minor however:\n\nChanges requested by Catalin / Will:\n\n * ABI change: Zero SVE regs on syscall entry:\n\n Refactoring since v2 that allowed discard to be explicitly requested\n has been dropped, since now discard has already happened at syscall\n entry in the relevant scenarios.\n\n * Delete a comment that that is no longer appropriate: there can no\n longer be a pending discard.\n\n It still makes reasonable sense to write the FPSIMD/SVE state back\n to thread_struct on the common path though.\n---\n arch/arm64/include/asm/fpsimd.h | 1 +\n arch/arm64/kernel/fpsimd.c | 55 ++++++++++---\n arch/arm64/kernel/signal.c | 167 ++++++++++++++++++++++++++++++++++++++--\n arch/arm64/kernel/signal32.c | 2 +-\n 4 files changed, 206 insertions(+), 19 deletions(-)","diff":"diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\nindex 5655fe1..9bbd74c 100644\n--- a/arch/arm64/include/asm/fpsimd.h\n+++ b/arch/arm64/include/asm/fpsimd.h\n@@ -63,6 +63,7 @@ extern void fpsimd_load_state(struct fpsimd_state *state);\n extern void fpsimd_thread_switch(struct task_struct *next);\n extern void fpsimd_flush_thread(void);\n \n+extern void fpsimd_signal_preserve_current_state(void);\n extern void fpsimd_preserve_current_state(void);\n extern void fpsimd_restore_current_state(void);\n extern void fpsimd_update_current_state(struct fpsimd_state *state);\ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 2b691d1..5063476 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -298,6 +298,32 @@ static void fpsimd_to_sve(struct task_struct *task)\n \t\t sizeof(fst->vregs[i]));\n }\n \n+/*\n+ * Transfer the SVE state in task->thread.sve_state to\n+ * task->thread.fpsimd_state.\n+ *\n+ * Task can be a non-runnable task, or current. In the latter case,\n+ * softirqs (and preemption) must be disabled.\n+ * task->thread.sve_state must point to at least sve_state_size(task)\n+ * bytes of allocated kernel memory.\n+ * task->thread.sve_state must be up to date before calling this function.\n+ */\n+static void sve_to_fpsimd(struct task_struct *task)\n+{\n+\tunsigned int vq;\n+\tvoid const *sst = task->thread.sve_state;\n+\tstruct fpsimd_state *fst = &task->thread.fpsimd_state;\n+\tunsigned int i;\n+\n+\tif (!system_supports_sve())\n+\t\treturn;\n+\n+\tvq = sve_vq_from_vl(task->thread.sve_vl);\n+\tfor (i = 0; i < 32; ++i)\n+\t\tmemcpy(&fst->vregs[i], ZREG(sst, vq, i),\n+\t\t sizeof(fst->vregs[i]));\n+}\n+\n #ifdef CONFIG_ARM64_SVE\n \n /*\n@@ -499,9 +525,6 @@ void fpsimd_flush_thread(void)\n /*\n * Save the userland FPSIMD state of 'current' to memory, but only if the state\n * currently held in the registers does in fact belong to 'current'\n- *\n- * Currently, SVE tasks can't exist, so just WARN in that case.\n- * Subsequent patches will add full SVE support here.\n */\n void fpsimd_preserve_current_state(void)\n {\n@@ -509,16 +532,23 @@ void fpsimd_preserve_current_state(void)\n \t\treturn;\n \n \tlocal_bh_disable();\n-\n-\tif (!test_thread_flag(TIF_FOREIGN_FPSTATE))\n-\t\tfpsimd_save_state(¤t->thread.fpsimd_state);\n-\n-\tWARN_ON_ONCE(test_and_clear_thread_flag(TIF_SVE));\n-\n+\ttask_fpsimd_save();\n \tlocal_bh_enable();\n }\n \n /*\n+ * Like fpsimd_preserve_current_state(), but ensure that\n+ * current->thread.fpsimd_state is updated so that it can be copied to\n+ * the signal frame.\n+ */\n+void fpsimd_signal_preserve_current_state(void)\n+{\n+\tfpsimd_preserve_current_state();\n+\tif (system_supports_sve() && test_thread_flag(TIF_SVE))\n+\t\tsve_to_fpsimd(current);\n+}\n+\n+/*\n * Load the userland FPSIMD state of 'current' from memory, but only if the\n * FPSIMD state already held in the registers is /not/ the most recent FPSIMD\n * state of 'current'\n@@ -553,7 +583,12 @@ void fpsimd_update_current_state(struct fpsimd_state *state)\n \n \tlocal_bh_disable();\n \n-\tfpsimd_load_state(state);\n+\tif (system_supports_sve() && test_thread_flag(TIF_SVE)) {\n+\t\tcurrent->thread.fpsimd_state = *state;\n+\t\tfpsimd_to_sve(current);\n+\t}\n+\ttask_fpsimd_load();\n+\n \tif (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {\n \t\tstruct fpsimd_state *st = ¤t->thread.fpsimd_state;\n \ndiff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c\nindex 0bdc96c..79bc55a 100644\n--- a/arch/arm64/kernel/signal.c\n+++ b/arch/arm64/kernel/signal.c\n@@ -63,6 +63,7 @@ struct rt_sigframe_user_layout {\n \n \tunsigned long fpsimd_offset;\n \tunsigned long esr_offset;\n+\tunsigned long sve_offset;\n \tunsigned long extra_offset;\n \tunsigned long end_offset;\n };\n@@ -179,9 +180,6 @@ static int preserve_fpsimd_context(struct fpsimd_context __user *ctx)\n \tstruct fpsimd_state *fpsimd = ¤t->thread.fpsimd_state;\n \tint err;\n \n-\t/* dump the hardware registers to the fpsimd_state structure */\n-\tfpsimd_preserve_current_state();\n-\n \t/* copy the FP and status/control registers */\n \terr = __copy_to_user(ctx->vregs, fpsimd->vregs, sizeof(fpsimd->vregs));\n \t__put_user_error(fpsimd->fpsr, &ctx->fpsr, err);\n@@ -214,6 +212,8 @@ static int restore_fpsimd_context(struct fpsimd_context __user *ctx)\n \t__get_user_error(fpsimd.fpsr, &ctx->fpsr, err);\n \t__get_user_error(fpsimd.fpcr, &ctx->fpcr, err);\n \n+\tclear_thread_flag(TIF_SVE);\n+\n \t/* load the hardware registers from the fpsimd_state structure */\n \tif (!err)\n \t\tfpsimd_update_current_state(&fpsimd);\n@@ -221,10 +221,118 @@ static int restore_fpsimd_context(struct fpsimd_context __user *ctx)\n \treturn err ? -EFAULT : 0;\n }\n \n+\n struct user_ctxs {\n \tstruct fpsimd_context __user *fpsimd;\n+\tstruct sve_context __user *sve;\n };\n \n+#ifdef CONFIG_ARM64_SVE\n+\n+static int preserve_sve_context(struct sve_context __user *ctx)\n+{\n+\tint err = 0;\n+\tu16 reserved[ARRAY_SIZE(ctx->__reserved)];\n+\tunsigned int vl = current->thread.sve_vl;\n+\tunsigned int vq = 0;\n+\n+\tif (test_thread_flag(TIF_SVE))\n+\t\tvq = sve_vq_from_vl(vl);\n+\n+\tmemset(reserved, 0, sizeof(reserved));\n+\n+\t__put_user_error(SVE_MAGIC, &ctx->head.magic, err);\n+\t__put_user_error(round_up(SVE_SIG_CONTEXT_SIZE(vq), 16),\n+\t\t\t &ctx->head.size, err);\n+\t__put_user_error(vl, &ctx->vl, err);\n+\tBUILD_BUG_ON(sizeof(ctx->__reserved) != sizeof(reserved));\n+\terr |= copy_to_user(&ctx->__reserved, reserved, sizeof(reserved));\n+\n+\tif (vq) {\n+\t\t/*\n+\t\t * This assumes that the SVE state has already been saved to\n+\t\t * the task struct by calling preserve_fpsimd_context().\n+\t\t */\n+\t\terr |= copy_to_user((char __user *)ctx + SVE_SIG_REGS_OFFSET,\n+\t\t\t\t current->thread.sve_state,\n+\t\t\t\t SVE_SIG_REGS_SIZE(vq));\n+\t}\n+\n+\treturn err ? -EFAULT : 0;\n+}\n+\n+static int restore_sve_fpsimd_context(struct user_ctxs *user)\n+{\n+\tint err;\n+\tunsigned int vq;\n+\tstruct fpsimd_state fpsimd;\n+\tstruct sve_context sve;\n+\n+\tif (__copy_from_user(&sve, user->sve, sizeof(sve)))\n+\t\treturn -EFAULT;\n+\n+\tif (sve.vl != current->thread.sve_vl)\n+\t\treturn -EINVAL;\n+\n+\tif (sve.head.size <= sizeof(*user->sve)) {\n+\t\tclear_thread_flag(TIF_SVE);\n+\t\tgoto fpsimd_only;\n+\t}\n+\n+\tvq = sve_vq_from_vl(sve.vl);\n+\n+\tif (sve.head.size < SVE_SIG_CONTEXT_SIZE(vq))\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * Careful: we are about __copy_from_user() directly into\n+\t * thread.sve_state with preemption enabled, so protection is\n+\t * needed to prevent a racing context switch from writing stale\n+\t * registers back over the new data.\n+\t */\n+\n+\tfpsimd_flush_task_state(current);\n+\tbarrier();\n+\t/* From now, fpsimd_thread_switch() won't clear TIF_FOREIGN_FPSTATE */\n+\n+\tset_thread_flag(TIF_FOREIGN_FPSTATE);\n+\tbarrier();\n+\t/* From now, fpsimd_thread_switch() won't touch thread.sve_state */\n+\n+\tsve_alloc(current);\n+\terr = __copy_from_user(current->thread.sve_state,\n+\t\t\t (char __user const *)user->sve +\n+\t\t\t\t\tSVE_SIG_REGS_OFFSET,\n+\t\t\t SVE_SIG_REGS_SIZE(vq));\n+\tif (err)\n+\t\treturn err;\n+\n+\tset_thread_flag(TIF_SVE);\n+\n+fpsimd_only:\n+\t/* copy the FP and status/control registers */\n+\t/* restore_sigframe() already checked that user->fpsimd != NULL. */\n+\terr = __copy_from_user(fpsimd.vregs, user->fpsimd->vregs,\n+\t\t\t sizeof(fpsimd.vregs));\n+\t__get_user_error(fpsimd.fpsr, &user->fpsimd->fpsr, err);\n+\t__get_user_error(fpsimd.fpcr, &user->fpsimd->fpcr, err);\n+\n+\t/* load the hardware registers from the fpsimd_state structure */\n+\tif (!err)\n+\t\tfpsimd_update_current_state(&fpsimd);\n+\n+\treturn err;\n+}\n+\n+#else /* ! CONFIG_ARM64_SVE */\n+\n+/* Turn any non-optimised out attempts to use these into a link error: */\n+extern int preserve_sve_context(void __user *ctx);\n+extern int restore_sve_fpsimd_context(struct user_ctxs *user);\n+\n+#endif /* ! CONFIG_ARM64_SVE */\n+\n+\n static int parse_user_sigframe(struct user_ctxs *user,\n \t\t\t struct rt_sigframe __user *sf)\n {\n@@ -237,6 +345,7 @@ static int parse_user_sigframe(struct user_ctxs *user,\n \tchar const __user *const sfp = (char const __user *)sf;\n \n \tuser->fpsimd = NULL;\n+\tuser->sve = NULL;\n \n \tif (!IS_ALIGNED((unsigned long)base, 16))\n \t\tgoto invalid;\n@@ -287,6 +396,19 @@ static int parse_user_sigframe(struct user_ctxs *user,\n \t\t\t/* ignore */\n \t\t\tbreak;\n \n+\t\tcase SVE_MAGIC:\n+\t\t\tif (!system_supports_sve())\n+\t\t\t\tgoto invalid;\n+\n+\t\t\tif (user->sve)\n+\t\t\t\tgoto invalid;\n+\n+\t\t\tif (size < sizeof(*user->sve))\n+\t\t\t\tgoto invalid;\n+\n+\t\t\tuser->sve = (struct sve_context __user *)head;\n+\t\t\tbreak;\n+\n \t\tcase EXTRA_MAGIC:\n \t\t\tif (have_extra_context)\n \t\t\t\tgoto invalid;\n@@ -359,9 +481,6 @@ static int parse_user_sigframe(struct user_ctxs *user,\n \t}\n \n done:\n-\tif (!user->fpsimd)\n-\t\tgoto invalid;\n-\n \treturn 0;\n \n invalid:\n@@ -395,8 +514,19 @@ static int restore_sigframe(struct pt_regs *regs,\n \tif (err == 0)\n \t\terr = parse_user_sigframe(&user, sf);\n \n-\tif (err == 0)\n-\t\terr = restore_fpsimd_context(user.fpsimd);\n+\tif (err == 0) {\n+\t\tif (!user.fpsimd)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (user.sve) {\n+\t\t\tif (!system_supports_sve())\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\terr = restore_sve_fpsimd_context(&user);\n+\t\t} else {\n+\t\t\terr = restore_fpsimd_context(user.fpsimd);\n+\t\t}\n+\t}\n \n \treturn err;\n }\n@@ -455,6 +585,18 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user)\n \t\t\treturn err;\n \t}\n \n+\tif (system_supports_sve()) {\n+\t\tunsigned int vq = 0;\n+\n+\t\tif (test_thread_flag(TIF_SVE))\n+\t\t\tvq = sve_vq_from_vl(current->thread.sve_vl);\n+\n+\t\terr = sigframe_alloc(user, &user->sve_offset,\n+\t\t\t\t SVE_SIG_CONTEXT_SIZE(vq));\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n \treturn sigframe_alloc_end(user);\n }\n \n@@ -496,6 +638,13 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user,\n \t\t__put_user_error(current->thread.fault_code, &esr_ctx->esr, err);\n \t}\n \n+\t/* Scalable Vector Extension state, if present */\n+\tif (system_supports_sve() && err == 0 && user->sve_offset) {\n+\t\tstruct sve_context __user *sve_ctx =\n+\t\t\tapply_user_offset(user, user->sve_offset);\n+\t\terr |= preserve_sve_context(sve_ctx);\n+\t}\n+\n \tif (err == 0 && user->extra_offset) {\n \t\tchar __user *sfp = (char __user *)user->sigframe;\n \t\tchar __user *userp =\n@@ -595,6 +744,8 @@ static int setup_rt_frame(int usig, struct ksignal *ksig, sigset_t *set,\n \tstruct rt_sigframe __user *frame;\n \tint err = 0;\n \n+\tfpsimd_signal_preserve_current_state();\n+\n \tif (get_sigframe(&user, ksig, regs))\n \t\treturn 1;\n \ndiff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c\nindex e09bf5d..22711ee 100644\n--- a/arch/arm64/kernel/signal32.c\n+++ b/arch/arm64/kernel/signal32.c\n@@ -239,7 +239,7 @@ static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)\n \t * Note that this also saves V16-31, which aren't visible\n \t * in AArch32.\n \t */\n-\tfpsimd_preserve_current_state();\n+\tfpsimd_signal_preserve_current_state();\n \n \t/* Place structure header on the stack */\n \t__put_user_error(magic, &frame->magic, err);\n","prefixes":["v4","13/28"]}