{"id":831215,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831215/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-12-git-send-email-Dave.Martin@arm.com/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.2/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509101470-7881-12-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-10-27T10:50:53","name":"[v4,11/28] arm64/sve: Core task context handling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8f5f1297dd798b075435073f91f9338344d1e3ab","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-12-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":10555,"url":"http://patchwork.ozlabs.org/api/1.2/series/10555/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=10555","date":"2017-10-27T10:50:42","name":"ARM Scalable Vector Extension (SVE)","version":4,"mbox":"http://patchwork.ozlabs.org/series/10555/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831215/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831215/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; 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b=mi5BA3ppYM5GyHy7GI8mB+UoyM452wDcUehuURiwbjk\n\tFOtBcQg1GB3Q0CtrqbbIVbpnTpwNDYTSOWMREpWwR4RtLnOW6IEP/lc5/RSdV1QN\n\ttaa6GyDwmoCFBD/Xe9mBWblMGBQvwFKn8Avcs4PXGpYYT7vqqDeTisXLE6usZV5A\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=sDzldIyk7D8o9rfZU8A7xALK/Ag=; b=DWckOTmx/bFFRqqxq\n\tkYooCR5feTtB/SOjcZB3BkS3IUvgv4qjhzoDoBOiCJ8SWq4TiknTuD+qMoTazZqZ\n\tRkNtTcGg6Ym+9PWDcuFu7az/TjTpdoqyCK63/wSku1VN6u0JfL9jz/KKOZzqFM5p\n\tvi5MXuc0TTNoUESr+jInWzYblQ=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=general-purpose,\n\tgeneralpurpose, scheduled, cease","X-HELO":"foss.arm.com","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas , Will Deacon\n\t, \tArd Biesheuvel ,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= ,\n\tSzabolcs Nagy , Okamoto Takayuki\n\t, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v4 11/28] arm64/sve: Core task context handling","Date":"Fri, 27 Oct 2017 11:50:53 +0100","Message-Id":"<1509101470-7881-12-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"This patch adds the core support for switching and managing the SVE\narchitectural state of user tasks.\n\nCalls to the existing FPSIMD low-level save/restore functions are\nfactored out as new functions task_fpsimd_{save,load}(), since SVE\nnow dynamically may or may not need to be handled at these points\ndepending on the kernel configuration, hardware features discovered\nat boot, and the runtime state of the task. To make these\ndecisions as fast as possible, const cpucaps are used where\nfeasible, via the system_supports_sve() helper.\n\nThe SVE registers are only tracked for threads that have explicitly\nused SVE, indicated by the new thread flag TIF_SVE. Otherwise, the\nFPSIMD view of the architectural state is stored in\nthread.fpsimd_state as usual.\n\nWhen in use, the SVE registers are not stored directly in\nthread_struct due to their potentially large and variable size.\nBecause the task_struct slab allocator must be configured very\nearly during kernel boot, it is also tricky to configure it\ncorrectly to match the maximum vector length provided by the\nhardware, since this depends on examining secondary CPUs as well as\nthe primary. Instead, a pointer sve_state in thread_struct points\nto a dynamically allocated buffer containing the SVE register data,\nand code is added to allocate and free this buffer at appropriate\ntimes.\n\nTIF_SVE is set when taking an SVE access trap from userspace, if\nsuitable hardware support has been detected. This enables SVE for\nthe thread: a subsequent return to userspace will disable the trap\naccordingly. If such a trap is taken without sufficient system-\nwide hardware support, SIGILL is sent to the thread instead as if\nan undefined instruction had been executed: this may happen if\nuserspace tries to use SVE in a system where not all CPUs support\nit for example.\n\nThe kernel will clear TIF_SVE and disable SVE for the thread\nwhenever an explicit syscall is made by userspace. For backwards\ncompatibility reasons and conformance with the spirit of the base\nAArch64 procedure call standard, the subset of the SVE register\nstate that aliases the FPSIMD registers is still preserved across a\nsyscall even if this happens. The remainder of the SVE register\nstate logically becomes zero at syscall entry, though the actual\nzeroing work is currently deferred until the thread next tries to\nuse SVE, causing another trap to the kernel. This implementation\nis suboptimal: in the future, the fastpath case may be optimised\nto zero the registers in-place and leave SVE enabled for the task,\nwhere beneficial.\n\nTIF_SVE is also cleared in the following slowpath cases, which are\ntaken as reasonable hints that the task may no longer use SVE:\n * exec\n * fork and clone\n\nCode is added to sync data between thread.fpsimd_state and\nthread.sve_state whenever enabling/disabling SVE, in a manner\nconsistent with the SVE architectural programmer's model.\n\nSigned-off-by: Dave Martin \nCc: Ard Biesheuvel \nCc: Alex BennĂ©e \n\n---\n\nChanges since v3\n----------------\n\nChanges requested by Catalin Marinas:\n\n * Change static __maybe_unused functions to static inlines.\n\n * Move fpsimd_release_thread() to the arch_release_task_struct() path.\n\n This avoids any need to worry about preemption.\n\n A declaration for arch_release_task_struct() is added to\n to help guard against inconsistent prototypes,\n though this is not required and the code would work without it.\n\n (thread_info.h is already included by the relevant code code, and\n arch/sh uses the same header).\n\n * Added comments to explain the meaning of TIF_SVE.\n\n * ABI change: Zero SVE regs on syscall entry.\n\n Detailed rationale:\n\nAs currently documented, no guarantee is made about what a user\ntask sees in the SVE registers after a syscall, except that V0-V31\n(corresponding to Z0-Z31 bits [127:0]) are preserved.\n\nThe actual kernel behaviour currently implemented is that the SVE\nregisters are zeroed if a context switch or signal delivery occurs\nduring a syscall. After a fork() or clone(), the SVE registers\nof the child task are zeroed also. The SVE registers are otherwise\npreserved. Flexibility is retained in the ABI about the exact\ncriteria for the decision.\n\nThere are some potential problems with this approach.\n\nSyscall impact\n--------------\n\nWill, Catalin and Mark have expressed concerns about the risk of\ncreating de facto ABI here: in scenarios or workloads where a\ncontext switch never occurs or is very unlikely, userspace may\nlearn to rely on preservation of the SVE registers across certain\nsyscalls.\n\nIt is difficult to assess the impact of this: the syscall ABI is\nnot a general-purpose interface, since it is usually hidden behind\nlibc wrappers: direct invocation of SVC is discouraged. However,\nspecialised runtimes, statically linked programs and binary blobs\nmay bake in direct syscalls that make bad assumptions.\n\nConversely, the relative cost of zeroing the SVE regs to mitigate\nagainst this also cannot be well characterised until SVE hardware\nexists.\n\nptrace impact\n-------------\n\nThe current implementation can discard and zero the SVE registers\nat any point during a syscall, including before, after or between\nptrace traps inside a single syscall. This means that setting the\nSVE registers through PTRACE_SETREGSET will often not do what the\nuser expects: the new register values are only guaranteed to\nsurvive as far as userspace if set from an asynchronous\nsignal-delivery-stop (e.g., breakpoint, SEGV or asynchronous signal\ndelivered outside syscall context).\n\nThis is consistent with the currently documented SVE user ABI, but\nlikely to be surprising for a debugger user, since setting most\nregisters of a tracee doesn't behave in this way.\n\nThis patch\n----------\n\nThe common syscall entry path is modified to forcibly discard SVE,\nand the discard logic elsewhere is removed.\n\nThis means that there is a mandatory additional trap to the kernel\nwhen a user task tries to use SVE again after a syscall. This can\nbe expensive for programs that use SVE heavily around syscalls, but\ncan be optimised later.\n\nBecause all ptrace traps occur after syscall entry, this also means\nthat no discard will occur after SVE registers are set through\nptrace, until the task next passes through userspace and does\nanother syscall. The only exception to this is in fork()/clone()\nwhere forced discard still occurs: however, this is likely to be\nencountered less frequently by debugger users.\n\nThis ABI change will commit the kernel to some extra cost: at least\nsome thread flag manipulation, conditional branching and\n\n\tmov\tv0.16b, v0.16b\n\tmov\tv1.16b, v1.16b\n\t// ...\n\tmov \tv31.16b, v31.16b\n\tpfalse\tp0.b\n\t// ...\n\tpfalse\tp15.b\n\twrffr\tp0.b\n\n(or equivalent) on the syscall fast path, for SVE tasks.\n\nFor now this patch requires trap + memset() + reload, so is\nsignificantly more expensive.\n---\n arch/arm64/include/asm/fpsimd.h | 16 ++\n arch/arm64/include/asm/processor.h | 2 +\n arch/arm64/include/asm/thread_info.h | 4 +\n arch/arm64/include/asm/traps.h | 2 +\n arch/arm64/kernel/entry.S | 39 ++++-\n arch/arm64/kernel/fpsimd.c | 324 ++++++++++++++++++++++++++++++++++-\n arch/arm64/kernel/process.c | 24 +++\n arch/arm64/kernel/traps.c | 6 +-\n 8 files changed, 406 insertions(+), 11 deletions(-)","diff":"diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\nindex 026a7c7..5655fe1 100644\n--- a/arch/arm64/include/asm/fpsimd.h\n+++ b/arch/arm64/include/asm/fpsimd.h\n@@ -20,6 +20,8 @@\n \n #ifndef __ASSEMBLY__\n \n+#include \n+\n /*\n * FP/SIMD storage area has:\n * - FPSR and FPCR\n@@ -72,6 +74,20 @@ extern void sve_load_state(void const *state, u32 const *pfpsr,\n \t\t\t unsigned long vq_minus_1);\n extern unsigned int sve_get_vl(void);\n \n+#ifdef CONFIG_ARM64_SVE\n+\n+extern size_t sve_state_size(struct task_struct const *task);\n+\n+extern void sve_alloc(struct task_struct *task);\n+extern void fpsimd_release_task(struct task_struct *task);\n+\n+#else /* ! CONFIG_ARM64_SVE */\n+\n+static inline void sve_alloc(struct task_struct *task) { }\n+static inline void fpsimd_release_task(struct task_struct *task) { }\n+\n+#endif /* ! CONFIG_ARM64_SVE */\n+\n /* For use by EFI runtime services calls only */\n extern void __efi_fpsimd_begin(void);\n extern void __efi_fpsimd_end(void);\ndiff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h\nindex 7dddca2..e2f575d 100644\n--- a/arch/arm64/include/asm/processor.h\n+++ b/arch/arm64/include/asm/processor.h\n@@ -105,6 +105,8 @@ struct thread_struct {\n \tunsigned long\t\ttp2_value;\n #endif\n \tstruct fpsimd_state\tfpsimd_state;\n+\tvoid\t\t\t*sve_state;\t/* SVE registers, if any */\n+\tunsigned int\t\tsve_vl;\t\t/* SVE vector length */\n \tunsigned long\t\tfault_address;\t/* fault info */\n \tunsigned long\t\tfault_code;\t/* ESR_EL1 value */\n \tstruct debug_info\tdebug;\t\t/* debugging */\ndiff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h\nindex ddded64..92b7b48 100644\n--- a/arch/arm64/include/asm/thread_info.h\n+++ b/arch/arm64/include/asm/thread_info.h\n@@ -63,6 +63,8 @@ struct thread_info {\n void arch_setup_new_exec(void);\n #define arch_setup_new_exec arch_setup_new_exec\n \n+void arch_release_task_struct(struct task_struct *tsk);\n+\n #endif\n \n /*\n@@ -92,6 +94,7 @@ void arch_setup_new_exec(void);\n #define TIF_RESTORE_SIGMASK\t20\n #define TIF_SINGLESTEP\t\t21\n #define TIF_32BIT\t\t22\t/* 32bit process */\n+#define TIF_SVE\t\t\t23\t/* Scalable Vector Extension in use */\n \n #define _TIF_SIGPENDING\t\t(1 << TIF_SIGPENDING)\n #define _TIF_NEED_RESCHED\t(1 << TIF_NEED_RESCHED)\n@@ -105,6 +108,7 @@ void arch_setup_new_exec(void);\n #define _TIF_UPROBE\t\t(1 << TIF_UPROBE)\n #define _TIF_FSCHECK\t\t(1 << TIF_FSCHECK)\n #define _TIF_32BIT\t\t(1 << TIF_32BIT)\n+#define _TIF_SVE\t\t(1 << TIF_SVE)\n \n #define _TIF_WORK_MASK\t\t(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \\\n \t\t\t\t _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \\\ndiff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h\nindex 45e3da3..1696f9d 100644\n--- a/arch/arm64/include/asm/traps.h\n+++ b/arch/arm64/include/asm/traps.h\n@@ -34,6 +34,8 @@ struct undef_hook {\n \n void register_undef_hook(struct undef_hook *hook);\n void unregister_undef_hook(struct undef_hook *hook);\n+void force_signal_inject(int signal, int code, struct pt_regs *regs,\n+\t\t\t unsigned long address);\n \n void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr);\n \ndiff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S\nindex f5e851e..56e848f 100644\n--- a/arch/arm64/kernel/entry.S\n+++ b/arch/arm64/kernel/entry.S\n@@ -607,6 +607,8 @@ el0_sync:\n \tb.eq\tel0_ia\n \tcmp\tx24, #ESR_ELx_EC_FP_ASIMD\t// FP/ASIMD access\n \tb.eq\tel0_fpsimd_acc\n+\tcmp\tx24, #ESR_ELx_EC_SVE\t\t// SVE access\n+\tb.eq\tel0_sve_acc\n \tcmp\tx24, #ESR_ELx_EC_FP_EXC64\t// FP/ASIMD exception\n \tb.eq\tel0_fpsimd_exc\n \tcmp\tx24, #ESR_ELx_EC_SYS64\t\t// configurable trap\n@@ -658,6 +660,7 @@ el0_svc_compat:\n \t/*\n \t * AArch32 syscall handling\n \t */\n+\tldr\tx16, [tsk, #TSK_TI_FLAGS]\t// load thread flags\n \tadrp\tstbl, compat_sys_call_table\t// load compat syscall table pointer\n \tmov\twscno, w7\t\t\t// syscall number in w7 (r7)\n \tmov wsc_nr, #__NR_compat_syscalls\n@@ -705,9 +708,19 @@ el0_fpsimd_acc:\n \tmov\tx1, sp\n \tbl\tdo_fpsimd_acc\n \tb\tret_to_user\n+el0_sve_acc:\n+\t/*\n+\t * Scalable Vector Extension access\n+\t */\n+\tenable_dbg_and_irq\n+\tct_user_exit\n+\tmov\tx0, x25\n+\tmov\tx1, sp\n+\tbl\tdo_sve_acc\n+\tb\tret_to_user\n el0_fpsimd_exc:\n \t/*\n-\t * Floating Point or Advanced SIMD exception\n+\t * Floating Point, Advanced SIMD or SVE exception\n \t */\n \tenable_dbg\n \tct_user_exit\n@@ -835,16 +848,36 @@ ENDPROC(ret_to_user)\n */\n \t.align\t6\n el0_svc:\n+\tldr\tx16, [tsk, #TSK_TI_FLAGS]\t// load thread flags\n \tadrp\tstbl, sys_call_table\t\t// load syscall table pointer\n \tmov\twscno, w8\t\t\t// syscall number in w8\n \tmov\twsc_nr, #__NR_syscalls\n+\n+#ifndef CONFIG_ARM64_SVE\n+\tb\tel0_svc_naked\n+#else\n+\ttbz\tx16, #TIF_SVE, el0_svc_naked\t// Skip unless TIF_SVE set:\n+\tbic\tx16, x16, #_TIF_SVE\t\t// discard SVE state\n+\tstr\tx16, [tsk, #TSK_TI_FLAGS]\n+\n+\t/*\n+\t * task_fpsimd_load() won't be called to update CPACR_EL1 in\n+\t * ret_to_user unless TIF_FOREIGN_FPSTATE is still set, which only\n+\t * happens if a context switch or kernel_neon_begin() or context\n+\t * modification (sigreturn, ptrace) intervenes.\n+\t * So, ensure that CPACR_EL1 is already correct for the fast-path case:\n+\t */\n+\tmrs\tx9, cpacr_el1\n+\tbic\tx9, x9, #CPACR_EL1_ZEN_EL0EN\t// disable SVE for el0\n+\tmsr\tcpacr_el1, x9\t\t\t// synchronised by eret to el0\n+#endif /* CONFIG_ARM64_SVE */\n+\n el0_svc_naked:\t\t\t\t\t// compat entry point\n \tstp\tx0, xscno, [sp, #S_ORIG_X0]\t// save the original x0 and syscall number\n \tenable_dbg_and_irq\n \tct_user_exit 1\n \n-\tldr\tx16, [tsk, #TSK_TI_FLAGS]\t// check for syscall hooks\n-\ttst\tx16, #_TIF_SYSCALL_WORK\n+\ttst\tx16, #_TIF_SYSCALL_WORK\t\t// check for syscall hooks\n \tb.ne\t__sys_trace\n \tcmp wscno, wsc_nr\t\t\t// check upper syscall limit\n \tb.hs\tni_sys\ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 7a865c8..0b15a594 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -18,18 +18,26 @@\n */\n \n #include \n+#include \n+#include \n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n+#include \n #include \n #include \n+#include \n \n #include \n #include \n #include \n+#include \n+#include \n+#include \n \n #define FPEXC_IOF\t(1 << 0)\n #define FPEXC_DZF\t(1 << 1)\n@@ -39,6 +47,8 @@\n #define FPEXC_IDF\t(1 << 7)\n \n /*\n+ * (Note: in this discussion, statements about FPSIMD apply equally to SVE.)\n+ *\n * In order to reduce the number of times the FPSIMD state is needlessly saved\n * and restored, we need to keep track of two things:\n * (a) for each task, we need to remember which CPU was the last one to have\n@@ -100,6 +110,279 @@\n static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);\n \n /*\n+ * Call __sve_free() directly only if you know task can't be scheduled\n+ * or preempted.\n+ */\n+static void __sve_free(struct task_struct *task)\n+{\n+\tkfree(task->thread.sve_state);\n+\ttask->thread.sve_state = NULL;\n+}\n+\n+static void sve_free(struct task_struct *task)\n+{\n+\tWARN_ON(test_tsk_thread_flag(task, TIF_SVE));\n+\n+\t__sve_free(task);\n+}\n+\n+\n+/* Offset of FFR in the SVE register dump */\n+static size_t sve_ffr_offset(int vl)\n+{\n+\treturn SVE_SIG_FFR_OFFSET(sve_vq_from_vl(vl)) - SVE_SIG_REGS_OFFSET;\n+}\n+\n+static void *sve_pffr(struct task_struct *task)\n+{\n+\treturn (char *)task->thread.sve_state +\n+\t\tsve_ffr_offset(task->thread.sve_vl);\n+}\n+\n+static void change_cpacr(u64 val, u64 mask)\n+{\n+\tu64 cpacr = read_sysreg(CPACR_EL1);\n+\tu64 new = (cpacr & ~mask) | val;\n+\n+\tif (new != cpacr)\n+\t\twrite_sysreg(new, CPACR_EL1);\n+}\n+\n+static void sve_user_disable(void)\n+{\n+\tchange_cpacr(0, CPACR_EL1_ZEN_EL0EN);\n+}\n+\n+static void sve_user_enable(void)\n+{\n+\tchange_cpacr(CPACR_EL1_ZEN_EL0EN, CPACR_EL1_ZEN_EL0EN);\n+}\n+\n+/*\n+ * TIF_SVE controls whether a task can use SVE without trapping while\n+ * in userspace, and also the way a task's FPSIMD/SVE state is stored\n+ * in thread_struct.\n+ *\n+ * The kernel uses this flag to track whether a user task is actively\n+ * using SVE, and therefore whether full SVE register state needs to\n+ * be tracked. If not, the cheaper FPSIMD context handling code can\n+ * be used instead of the more costly SVE equivalents.\n+ *\n+ * * TIF_SVE set:\n+ *\n+ * The task can execute SVE instructions while in userspace without\n+ * trapping to the kernel.\n+ *\n+ * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the\n+ * corresponding Zn), P0-P15 and FFR are encoded in in\n+ * task->thread.sve_state, formatted appropriately for vector\n+ * length task->thread.sve_vl.\n+ *\n+ * task->thread.sve_state must point to a valid buffer at least\n+ * sve_state_size(task) bytes in size.\n+ *\n+ * During any syscall, the kernel may optionally clear TIF_SVE and\n+ * discard the vector state except for the FPSIMD subset.\n+ *\n+ * * TIF_SVE clear:\n+ *\n+ * An attempt by the user task to execute an SVE instruction causes\n+ * do_sve_acc() to be called, which does some preparation and then\n+ * sets TIF_SVE.\n+ *\n+ * When stored, FPSIMD registers V0-V31 are encoded in\n+ * task->fpsimd_state; bits [max : 128] for each of Z0-Z31 are\n+ * logically zero but not stored anywhere; P0-P15 and FFR are not\n+ * stored and have unspecified values from userspace's point of\n+ * view. For hygiene purposes, the kernel zeroes them on next use,\n+ * but userspace is discouraged from relying on this.\n+ *\n+ * task->thread.sve_state does not need to be non-NULL, valid or any\n+ * particular size: it must not be dereferenced.\n+ *\n+ * * FPSR and FPCR are always stored in task->fpsimd_state irrespctive of\n+ * whether TIF_SVE is clear or set, since these are not vector length\n+ * dependent.\n+ */\n+\n+/*\n+ * Update current's FPSIMD/SVE registers from thread_struct.\n+ *\n+ * This function should be called only when the FPSIMD/SVE state in\n+ * thread_struct is known to be up to date, when preparing to enter\n+ * userspace.\n+ *\n+ * Softirqs (and preemption) must be disabled.\n+ */\n+static void task_fpsimd_load(void)\n+{\n+\tWARN_ON(!in_softirq() && !irqs_disabled());\n+\n+\tif (system_supports_sve() && test_thread_flag(TIF_SVE))\n+\t\tsve_load_state(sve_pffr(current),\n+\t\t\t ¤t->thread.fpsimd_state.fpsr,\n+\t\t\t sve_vq_from_vl(current->thread.sve_vl) - 1);\n+\telse\n+\t\tfpsimd_load_state(¤t->thread.fpsimd_state);\n+\n+\tif (system_supports_sve()) {\n+\t\t/* Toggle SVE trapping for userspace if needed */\n+\t\tif (test_thread_flag(TIF_SVE))\n+\t\t\tsve_user_enable();\n+\t\telse\n+\t\t\tsve_user_disable();\n+\n+\t\t/* Serialised by exception return to user */\n+\t}\n+}\n+\n+/*\n+ * Ensure current's FPSIMD/SVE storage in thread_struct is up to date\n+ * with respect to the CPU registers.\n+ *\n+ * Softirqs (and preemption) must be disabled.\n+ */\n+static void task_fpsimd_save(void)\n+{\n+\tWARN_ON(!in_softirq() && !irqs_disabled());\n+\n+\tif (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {\n+\t\tif (system_supports_sve() && test_thread_flag(TIF_SVE)) {\n+\t\t\tif (WARN_ON(sve_get_vl() != current->thread.sve_vl)) {\n+\t\t\t\t/*\n+\t\t\t\t * Can't save the user regs, so current would\n+\t\t\t\t * re-enter user with corrupt state.\n+\t\t\t\t * There's no way to recover, so kill it:\n+\t\t\t\t */\n+\t\t\t\tforce_signal_inject(\n+\t\t\t\t\tSIGKILL, 0, current_pt_regs(), 0);\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tsve_save_state(sve_pffr(current),\n+\t\t\t\t ¤t->thread.fpsimd_state.fpsr);\n+\t\t} else\n+\t\t\tfpsimd_save_state(¤t->thread.fpsimd_state);\n+\t}\n+}\n+\n+#define ZREG(sve_state, vq, n) ((char *)(sve_state) +\t\t\\\n+\t(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))\n+\n+/*\n+ * Transfer the FPSIMD state in task->thread.fpsimd_state to\n+ * task->thread.sve_state.\n+ *\n+ * Task can be a non-runnable task, or current. In the latter case,\n+ * softirqs (and preemption) must be disabled.\n+ * task->thread.sve_state must point to at least sve_state_size(task)\n+ * bytes of allocated kernel memory.\n+ * task->thread.fpsimd_state must be up to date before calling this function.\n+ */\n+static void fpsimd_to_sve(struct task_struct *task)\n+{\n+\tunsigned int vq;\n+\tvoid *sst = task->thread.sve_state;\n+\tstruct fpsimd_state const *fst = &task->thread.fpsimd_state;\n+\tunsigned int i;\n+\n+\tif (!system_supports_sve())\n+\t\treturn;\n+\n+\tvq = sve_vq_from_vl(task->thread.sve_vl);\n+\tfor (i = 0; i < 32; ++i)\n+\t\tmemcpy(ZREG(sst, vq, i), &fst->vregs[i],\n+\t\t sizeof(fst->vregs[i]));\n+}\n+\n+#ifdef CONFIG_ARM64_SVE\n+\n+/*\n+ * Return how many bytes of memory are required to store the full SVE\n+ * state for task, given task's currently configured vector length.\n+ */\n+size_t sve_state_size(struct task_struct const *task)\n+{\n+\treturn SVE_SIG_REGS_SIZE(sve_vq_from_vl(task->thread.sve_vl));\n+}\n+\n+/*\n+ * Ensure that task->thread.sve_state is allocated and sufficiently large.\n+ *\n+ * This function should be used only in preparation for replacing\n+ * task->thread.sve_state with new data. The memory is always zeroed\n+ * here to prevent stale data from showing through: this is done in\n+ * the interest of testability and predictability: except in the\n+ * do_sve_acc() case, there is no ABI requirement to hide stale data\n+ * written previously be task.\n+ */\n+void sve_alloc(struct task_struct *task)\n+{\n+\tif (task->thread.sve_state) {\n+\t\tmemset(task->thread.sve_state, 0, sve_state_size(current));\n+\t\treturn;\n+\t}\n+\n+\t/* This is a small allocation (maximum ~8KB) and Should Not Fail. */\n+\ttask->thread.sve_state =\n+\t\tkzalloc(sve_state_size(task), GFP_KERNEL);\n+\n+\t/*\n+\t * If future SVE revisions can have larger vectors though,\n+\t * this may cease to be true:\n+\t */\n+\tBUG_ON(!task->thread.sve_state);\n+}\n+\n+/*\n+ * Called from the put_task_struct() path, which cannot get here\n+ * unless dead_task is really dead and not schedulable.\n+ */\n+void fpsimd_release_task(struct task_struct *dead_task)\n+{\n+\t__sve_free(dead_task);\n+}\n+\n+#endif /* CONFIG_ARM64_SVE */\n+\n+/*\n+ * Trapped SVE access\n+ *\n+ * Storage is allocated for the full SVE state, the current FPSIMD\n+ * register contents are migrated across, and TIF_SVE is set so that\n+ * the SVE access trap will be disabled the next time this task\n+ * reaches ret_to_user.\n+ *\n+ * TIF_SVE should be clear on entry: otherwise, task_fpsimd_load()\n+ * would have disabled the SVE access trap for userspace during\n+ * ret_to_user, making an SVE access trap impossible in that case.\n+ */\n+void do_sve_acc(unsigned int esr, struct pt_regs *regs)\n+{\n+\t/* Even if we chose not to use SVE, the hardware could still trap: */\n+\tif (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) {\n+\t\tforce_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);\n+\t\treturn;\n+\t}\n+\n+\tsve_alloc(current);\n+\n+\tlocal_bh_disable();\n+\n+\ttask_fpsimd_save();\n+\tfpsimd_to_sve(current);\n+\n+\t/* Force ret_to_user to reload the registers: */\n+\tfpsimd_flush_task_state(current);\n+\tset_thread_flag(TIF_FOREIGN_FPSTATE);\n+\n+\tif (test_and_set_thread_flag(TIF_SVE))\n+\t\tWARN_ON(1); /* SVE access shouldn't have trapped */\n+\n+\tlocal_bh_enable();\n+}\n+\n+/*\n * Trapped FP/ASIMD access.\n */\n void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs)\n@@ -144,8 +427,8 @@ void fpsimd_thread_switch(struct task_struct *next)\n \t * the registers is in fact the most recent userland FPSIMD state of\n \t * 'current'.\n \t */\n-\tif (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))\n-\t\tfpsimd_save_state(¤t->thread.fpsimd_state);\n+\tif (current->mm)\n+\t\ttask_fpsimd_save();\n \n \tif (next->mm) {\n \t\t/*\n@@ -167,6 +450,8 @@ void fpsimd_thread_switch(struct task_struct *next)\n \n void fpsimd_flush_thread(void)\n {\n+\tint vl;\n+\n \tif (!system_supports_fpsimd())\n \t\treturn;\n \n@@ -174,6 +459,30 @@ void fpsimd_flush_thread(void)\n \n \tmemset(¤t->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));\n \tfpsimd_flush_task_state(current);\n+\n+\tif (system_supports_sve()) {\n+\t\tclear_thread_flag(TIF_SVE);\n+\t\tsve_free(current);\n+\n+\t\t/*\n+\t\t * Reset the task vector length as required.\n+\t\t * This is where we ensure that all user tasks have a valid\n+\t\t * vector length configured: no kernel task can become a user\n+\t\t * task without an exec and hence a call to this function.\n+\t\t * If a bug causes this to go wrong, we make some noise and\n+\t\t * try to fudge thread.sve_vl to a safe value here.\n+\t\t */\n+\t\tvl = current->thread.sve_vl;\n+\n+\t\tif (vl == 0)\n+\t\t\tvl = SVE_VL_MIN;\n+\n+\t\tif (WARN_ON(!sve_vl_valid(vl)))\n+\t\t\tvl = SVE_VL_MIN;\n+\n+\t\tcurrent->thread.sve_vl = vl;\n+\t}\n+\n \tset_thread_flag(TIF_FOREIGN_FPSTATE);\n \n \tlocal_bh_enable();\n@@ -182,6 +491,9 @@ void fpsimd_flush_thread(void)\n /*\n * Save the userland FPSIMD state of 'current' to memory, but only if the state\n * currently held in the registers does in fact belong to 'current'\n+ *\n+ * Currently, SVE tasks can't exist, so just WARN in that case.\n+ * Subsequent patches will add full SVE support here.\n */\n void fpsimd_preserve_current_state(void)\n {\n@@ -193,6 +505,8 @@ void fpsimd_preserve_current_state(void)\n \tif (!test_thread_flag(TIF_FOREIGN_FPSTATE))\n \t\tfpsimd_save_state(¤t->thread.fpsimd_state);\n \n+\tWARN_ON_ONCE(test_and_clear_thread_flag(TIF_SVE));\n+\n \tlocal_bh_enable();\n }\n \n@@ -211,7 +525,7 @@ void fpsimd_restore_current_state(void)\n \tif (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {\n \t\tstruct fpsimd_state *st = ¤t->thread.fpsimd_state;\n \n-\t\tfpsimd_load_state(st);\n+\t\ttask_fpsimd_load();\n \t\t__this_cpu_write(fpsimd_last_state, st);\n \t\tst->cpu = smp_processor_id();\n \t}\n@@ -380,8 +694,8 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,\n {\n \tswitch (cmd) {\n \tcase CPU_PM_ENTER:\n-\t\tif (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))\n-\t\t\tfpsimd_save_state(¤t->thread.fpsimd_state);\n+\t\tif (current->mm)\n+\t\t\ttask_fpsimd_save();\n \t\tthis_cpu_write(fpsimd_last_state, NULL);\n \t\tbreak;\n \tcase CPU_PM_EXIT:\ndiff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c\nindex 2dc0f84..9a3c561 100644\n--- a/arch/arm64/kernel/process.c\n+++ b/arch/arm64/kernel/process.c\n@@ -49,6 +49,7 @@\n #include \n #include \n #include \n+#include \n \n #include \n #include \n@@ -241,11 +242,27 @@ void release_thread(struct task_struct *dead_task)\n {\n }\n \n+void arch_release_task_struct(struct task_struct *tsk)\n+{\n+\tfpsimd_release_task(tsk);\n+}\n+\n+/*\n+ * src and dst may temporarily have aliased sve_state after task_struct\n+ * is copied. We cannot fix this properly here, because src may have\n+ * live SVE state and dst's thread_info may not exist yet, so tweaking\n+ * either src's or dst's TIF_SVE is not safe.\n+ *\n+ * The unaliasing is done in copy_thread() instead. This works because\n+ * dst is not schedulable or traceable until both of these functions\n+ * have been called.\n+ */\n int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)\n {\n \tif (current->mm)\n \t\tfpsimd_preserve_current_state();\n \t*dst = *src;\n+\n \treturn 0;\n }\n \n@@ -258,6 +275,13 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,\n \n \tmemset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));\n \n+\t/*\n+\t * Unalias p->thread.sve_state (if any) from the parent task\n+\t * and disable discard SVE state for p:\n+\t */\n+\tclear_tsk_thread_flag(p, TIF_SVE);\n+\tp->thread.sve_state = NULL;\n+\n \tif (likely(!(p->flags & PF_KTHREAD))) {\n \t\t*childregs = *current_pt_regs();\n \t\tchildregs->regs[0] = 0;\ndiff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c\nindex 20fbe42..7741dc9 100644\n--- a/arch/arm64/kernel/traps.c\n+++ b/arch/arm64/kernel/traps.c\n@@ -369,8 +369,8 @@ static int call_undef_hook(struct pt_regs *regs)\n \treturn fn ? fn(regs, instr) : 1;\n }\n \n-static void force_signal_inject(int signal, int code, struct pt_regs *regs,\n-\t\t\t\tunsigned long address)\n+void force_signal_inject(int signal, int code, struct pt_regs *regs,\n+\t\t\t unsigned long address)\n {\n \tsiginfo_t info;\n \tvoid __user *pc = (void __user *)instruction_pointer(regs);\n@@ -384,7 +384,7 @@ static void force_signal_inject(int signal, int code, struct pt_regs *regs,\n \t\tdesc = \"illegal memory access\";\n \t\tbreak;\n \tdefault:\n-\t\tdesc = \"bad mode\";\n+\t\tdesc = \"unknown or unrecoverable error\";\n \t\tbreak;\n \t}\n \n","prefixes":["v4","11/28"]}