{"id":831209,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831209/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-10-git-send-email-Dave.Martin@arm.com/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/1.2/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509101470-7881-10-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-10-27T10:50:51","name":"[v4,09/28] arm64/sve: Signal frame and context structure definition","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2a384325f817f431669b10c00b1319e3fdc10964","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-10-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":10556,"url":"http://patchwork.ozlabs.org/api/1.2/series/10556/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=10556","date":"2017-10-27T10:50:43","name":"ARM Scalable Vector Extension (SVE)","version":4,"mbox":"http://patchwork.ozlabs.org/series/10556/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831209/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831209/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Fri, 27 Oct 2017 03:51:35 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=QGNno1a5Xi7yqLw22x3qExQ+Ztb+Kix9NqRFewceE9Y=;\n\tb=mVxNmDZYRVXdt/\n\tCZjamOHhVdqPFJwX7YJhEQt+OSDERx47kIQhzyUck2Il13E8+N1nCJ5UzAyMZVWwB2HRd4UMz59f+\n\tty2jBv4tWeSuaL2C2B5i6wnH/0OqphpvsFSixHcsd+89CUMyhyagdRxEmOTVMCqGkR8UxaMKopm2I\n\tfgtZFRQ3+GfcYTYIgfdYYQzfXFGoeitKcJJZX1DrvXLGtptTKbDuVz3s0EAim27fR0rdoZ/WEMnc+\n\tVAwCxfOChhbueAWV5brpF+VaP2SybvNUaAUhr5L6YzMCsw4wmcWVQSnxWUol8c9GdBWIgFaM+ssXH\n\tJ4+VYQA2LgmqdyqgP+xg==;","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Subject":"[PATCH v4 09/28] arm64/sve: Signal frame and context structure\n\tdefinition","Date":"Fri, 27 Oct 2017 11:50:51 +0100","Message-Id":"<1509101470-7881-10-git-send-email-Dave.Martin@arm.com>","X-Mailer":"git-send-email 2.1.4","In-Reply-To":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171027_035200_075197_14C9DEFE ","X-CRM114-Status":"GOOD ( 16.57 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, Okamoto Takayuki ,\n\tlibc-alpha@sourceware.org, Ard Biesheuvel , \n\tSzabolcs Nagy , \n\tCatalin Marinas ,\n\tWill Deacon , =?utf-8?q?Alex_Benn=C3=A9e?=\n\t, kvmarm@lists.cs.columbia.edu","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"This patch defines the representation that will be used for the SVE\nregister state in the signal frame, and implements support for\nsaving and restoring the SVE registers around signals.\n\nThe same layout will also be used for the in-kernel task state.\n\nDue to the variability of the SVE vector length, it is not possible\nto define a fixed C struct to describe all the registers. Instead,\nMacros are defined in sigcontext.h to facilitate access to the\nparts of the structure.\n\nSigned-off-by: Dave Martin \nReviewed-by: Catalin Marinas \nCc: Alex Bennée \n---\n arch/arm64/include/uapi/asm/sigcontext.h | 117 ++++++++++++++++++++++++++++++-\n 1 file changed, 116 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h\nindex f0a76b9..7654a81 100644\n--- a/arch/arm64/include/uapi/asm/sigcontext.h\n+++ b/arch/arm64/include/uapi/asm/sigcontext.h\n@@ -16,6 +16,8 @@\n #ifndef _UAPI__ASM_SIGCONTEXT_H\n #define _UAPI__ASM_SIGCONTEXT_H\n \n+#ifndef __ASSEMBLY__\n+\n #include \n \n /*\n@@ -41,10 +43,11 @@ struct sigcontext {\n *\n *\t0x210\t\tfpsimd_context\n *\t 0x10\t\tesr_context\n+ *\t0x8a0\t\tsve_context (vl <= 64) (optional)\n *\t 0x20\t\textra_context (optional)\n *\t 0x10\t\tterminator (null _aarch64_ctx)\n *\n- *\t0xdb0\t\t(reserved for future allocation)\n+ *\t0x510\t\t(reserved for future allocation)\n *\n * New records that can exceed this space need to be opt-in for userspace, so\n * that an expanded signal frame is not generated unexpectedly. The mechanism\n@@ -116,4 +119,116 @@ struct extra_context {\n \t__u32 __reserved[3];\n };\n \n+#define SVE_MAGIC\t0x53564501\n+\n+struct sve_context {\n+\tstruct _aarch64_ctx head;\n+\t__u16 vl;\n+\t__u16 __reserved[3];\n+};\n+\n+#endif /* !__ASSEMBLY__ */\n+\n+/*\n+ * The SVE architecture leaves space for future expansion of the\n+ * vector length beyond its initial architectural limit of 2048 bits\n+ * (16 quadwords).\n+ */\n+#define SVE_VQ_BYTES\t\t16\t/* number of bytes per quadword */\n+\n+#define SVE_VQ_MIN\t\t1\n+#define SVE_VQ_MAX\t\t512\n+\n+#define SVE_VL_MIN\t\t(SVE_VQ_MIN * SVE_VQ_BYTES)\n+#define SVE_VL_MAX\t\t(SVE_VQ_MAX * SVE_VQ_BYTES)\n+\n+#define SVE_NUM_ZREGS\t\t32\n+#define SVE_NUM_PREGS\t\t16\n+\n+#define sve_vl_valid(vl) \\\n+\t((vl) % SVE_VQ_BYTES == 0 && (vl) >= SVE_VL_MIN && (vl) <= SVE_VL_MAX)\n+#define sve_vq_from_vl(vl)\t((vl) / SVE_VQ_BYTES)\n+#define sve_vl_from_vq(vq)\t((vq) * SVE_VQ_BYTES)\n+\n+/*\n+ * If the SVE registers are currently live for the thread at signal delivery,\n+ * sve_context.head.size >=\n+ *\tSVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl))\n+ * and the register data may be accessed using the SVE_SIG_*() macros.\n+ *\n+ * If sve_context.head.size <\n+ *\tSVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)),\n+ * the SVE registers were not live for the thread and no register data\n+ * is included: in this case, the SVE_SIG_*() macros should not be\n+ * used except for this check.\n+ *\n+ * The same convention applies when returning from a signal: a caller\n+ * will need to remove or resize the sve_context block if it wants to\n+ * make the SVE registers live when they were previously non-live or\n+ * vice-versa. This may require the the caller to allocate fresh\n+ * memory and/or move other context blocks in the signal frame.\n+ *\n+ * Changing the vector length during signal return is not permitted:\n+ * sve_context.vl must equal the thread's current vector length when\n+ * doing a sigreturn.\n+ *\n+ *\n+ * Note: for all these macros, the \"vq\" argument denotes the SVE\n+ * vector length in quadwords (i.e., units of 128 bits).\n+ *\n+ * The correct way to obtain vq is to use sve_vq_from_vl(vl). The\n+ * result is valid if and only if sve_vl_valid(vl) is true. This is\n+ * guaranteed for a struct sve_context written by the kernel.\n+ *\n+ *\n+ * Additional macros describe the contents and layout of the payload.\n+ * For each, SVE_SIG_x_OFFSET(args) is the start offset relative to\n+ * the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the\n+ * size in bytes:\n+ *\n+ *\tx\ttype\t\t\t\tdescription\n+ *\t-\t----\t\t\t\t-----------\n+ *\tREGS\t\t\t\t\tthe entire SVE context\n+ *\n+ *\tZREGS\t__uint128_t[SVE_NUM_ZREGS][vq]\tall Z-registers\n+ *\tZREG\t__uint128_t[vq]\t\t\tindividual Z-register Zn\n+ *\n+ *\tPREGS\tuint16_t[SVE_NUM_PREGS][vq]\tall P-registers\n+ *\tPREG\tuint16_t[vq]\t\t\tindividual P-register Pn\n+ *\n+ *\tFFR\tuint16_t[vq]\t\t\tfirst-fault status register\n+ *\n+ * Additional data might be appended in the future.\n+ */\n+\n+#define SVE_SIG_ZREG_SIZE(vq)\t((__u32)(vq) * SVE_VQ_BYTES)\n+#define SVE_SIG_PREG_SIZE(vq)\t((__u32)(vq) * (SVE_VQ_BYTES / 8))\n+#define SVE_SIG_FFR_SIZE(vq)\tSVE_SIG_PREG_SIZE(vq)\n+\n+#define SVE_SIG_REGS_OFFSET\t\t\t\t\t\\\n+\t((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1))\t\\\n+\t\t/ SVE_VQ_BYTES * SVE_VQ_BYTES)\n+\n+#define SVE_SIG_ZREGS_OFFSET\tSVE_SIG_REGS_OFFSET\n+#define SVE_SIG_ZREG_OFFSET(vq, n) \\\n+\t(SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREG_SIZE(vq) * (n))\n+#define SVE_SIG_ZREGS_SIZE(vq) \\\n+\t(SVE_SIG_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_SIG_ZREGS_OFFSET)\n+\n+#define SVE_SIG_PREGS_OFFSET(vq) \\\n+\t(SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREGS_SIZE(vq))\n+#define SVE_SIG_PREG_OFFSET(vq, n) \\\n+\t(SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREG_SIZE(vq) * (n))\n+#define SVE_SIG_PREGS_SIZE(vq) \\\n+\t(SVE_SIG_PREG_OFFSET(vq, SVE_NUM_PREGS) - SVE_SIG_PREGS_OFFSET(vq))\n+\n+#define SVE_SIG_FFR_OFFSET(vq) \\\n+\t(SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREGS_SIZE(vq))\n+\n+#define SVE_SIG_REGS_SIZE(vq) \\\n+\t(SVE_SIG_FFR_OFFSET(vq) + SVE_SIG_FFR_SIZE(vq) - SVE_SIG_REGS_OFFSET)\n+\n+#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))\n+\n+\n #endif /* _UAPI__ASM_SIGCONTEXT_H */\n","prefixes":["v4","09/28"]}