{"id":831206,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831206/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-7-git-send-email-Dave.Martin@arm.com/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.2/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1509101470-7881-7-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-10-27T10:50:48","name":"[v4,06/28] arm64/sve: System register and exception syndrome definitions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ce5738d199d93b3dd599d16cdecdef9c042d2425","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-7-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":10555,"url":"http://patchwork.ozlabs.org/api/1.2/series/10555/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=10555","date":"2017-10-27T10:50:42","name":"ARM Scalable Vector Extension (SVE)","version":4,"mbox":"http://patchwork.ozlabs.org/series/10555/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831206/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831206/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86448-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"sfoWHizT\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNggm15TTz9t30\n\tfor ;\n\tFri, 27 Oct 2017 21:52:35 +1100 (AEDT)","(qmail 116651 invoked by alias); 27 Oct 2017 10:51:35 -0000","(qmail 116592 invoked by uid 89); 27 Oct 2017 10:51:34 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=R/ku+q6gpQAN2/74OE3M5xs/n9WilMwlcsITM3GGTEO\n\t20oMfAn0GwPqbBnW/hmWj+pnW/KYkxuKtmeC1QyAhzoJUqv5kMy/Us46azapcPzd\n\tD9Yoc97ooHHrknJhIBiAgjrcinimUYcUIYP1A2YDPcQFX7KjtvwQ3uY+2/M5Rwwo\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=vvqBZSCDna8UCuN7EIWckxyzOYk=; b=sfoWHizTiSND4zzUr\n\tGpo+AG2DOfZZi8DIWPgbxWGZZbNtNZlzMXmczRTHKFAWdW1D9cwSUEmlKvGlb/Is\n\tlHHHECd6Jdk3a6poYhx17huQ2jq/g+NwhnG1bZN1yWaeRNJv8h0XAM/kUdzn2yJV\n\trwLmvCD4swlVUKM7yOq0j7Inh8=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=esr, 4326","X-HELO":"foss.arm.com","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas , Will Deacon\n\t, \tArd Biesheuvel ,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= ,\n\tSzabolcs Nagy , Okamoto Takayuki\n\t, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v4 06/28] arm64/sve: System register and exception syndrome\n\tdefinitions","Date":"Fri, 27 Oct 2017 11:50:48 +0100","Message-Id":"<1509101470-7881-7-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"The SVE architecture adds some system registers, ID register fields\nand a dedicated ESR exception class.\n\nThis patch adds the appropriate definitions that will be needed by\nthe kernel.\n\nSigned-off-by: Dave Martin \nReviewed-by: Alex Bennée \nReviewed-by: Catalin Marinas \n---\n arch/arm64/include/asm/esr.h | 3 ++-\n arch/arm64/include/asm/kvm_arm.h | 1 +\n arch/arm64/include/asm/sysreg.h | 21 +++++++++++++++++++++\n arch/arm64/kernel/traps.c | 1 +\n 4 files changed, 25 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h\nindex 66ed8b6..014d7d8 100644\n--- a/arch/arm64/include/asm/esr.h\n+++ b/arch/arm64/include/asm/esr.h\n@@ -43,7 +43,8 @@\n #define ESR_ELx_EC_HVC64\t(0x16)\n #define ESR_ELx_EC_SMC64\t(0x17)\n #define ESR_ELx_EC_SYS64\t(0x18)\n-/* Unallocated EC: 0x19 - 0x1E */\n+#define ESR_ELx_EC_SVE\t\t(0x19)\n+/* Unallocated EC: 0x1A - 0x1E */\n #define ESR_ELx_EC_IMP_DEF\t(0x1f)\n #define ESR_ELx_EC_IABT_LOW\t(0x20)\n #define ESR_ELx_EC_IABT_CUR\t(0x21)\ndiff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h\nindex 61d694c..dbf0537 100644\n--- a/arch/arm64/include/asm/kvm_arm.h\n+++ b/arch/arm64/include/asm/kvm_arm.h\n@@ -185,6 +185,7 @@\n #define CPTR_EL2_TCPAC\t(1 << 31)\n #define CPTR_EL2_TTA\t(1 << 20)\n #define CPTR_EL2_TFP\t(1 << CPTR_EL2_TFP_SHIFT)\n+#define CPTR_EL2_TZ\t(1 << 8)\n #define CPTR_EL2_DEFAULT\t0x000033ff\n \n /* Hyp Debug Configuration Register bits */\ndiff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h\nindex 609d59af..08cc885 100644\n--- a/arch/arm64/include/asm/sysreg.h\n+++ b/arch/arm64/include/asm/sysreg.h\n@@ -145,6 +145,7 @@\n \n #define SYS_ID_AA64PFR0_EL1\t\tsys_reg(3, 0, 0, 4, 0)\n #define SYS_ID_AA64PFR1_EL1\t\tsys_reg(3, 0, 0, 4, 1)\n+#define SYS_ID_AA64ZFR0_EL1\t\tsys_reg(3, 0, 0, 4, 4)\n \n #define SYS_ID_AA64DFR0_EL1\t\tsys_reg(3, 0, 0, 5, 0)\n #define SYS_ID_AA64DFR1_EL1\t\tsys_reg(3, 0, 0, 5, 1)\n@@ -163,6 +164,8 @@\n #define SYS_ACTLR_EL1\t\t\tsys_reg(3, 0, 1, 0, 1)\n #define SYS_CPACR_EL1\t\t\tsys_reg(3, 0, 1, 0, 2)\n \n+#define SYS_ZCR_EL1\t\t\tsys_reg(3, 0, 1, 2, 0)\n+\n #define SYS_TTBR0_EL1\t\t\tsys_reg(3, 0, 2, 0, 0)\n #define SYS_TTBR1_EL1\t\t\tsys_reg(3, 0, 2, 0, 1)\n #define SYS_TCR_EL1\t\t\tsys_reg(3, 0, 2, 0, 2)\n@@ -346,6 +349,8 @@\n \n #define SYS_PMCCFILTR_EL0\t\tsys_reg (3, 3, 14, 15, 7)\n \n+#define SYS_ZCR_EL2\t\t\tsys_reg(3, 4, 1, 2, 0)\n+\n #define SYS_DACR32_EL2\t\t\tsys_reg(3, 4, 3, 0, 0)\n #define SYS_IFSR32_EL2\t\t\tsys_reg(3, 4, 5, 0, 1)\n #define SYS_FPEXC32_EL2\t\t\tsys_reg(3, 4, 5, 3, 0)\n@@ -432,6 +437,7 @@\n #define ID_AA64ISAR1_DPB_SHIFT\t\t0\n \n /* id_aa64pfr0 */\n+#define ID_AA64PFR0_SVE_SHIFT\t\t32\n #define ID_AA64PFR0_GIC_SHIFT\t\t24\n #define ID_AA64PFR0_ASIMD_SHIFT\t\t20\n #define ID_AA64PFR0_FP_SHIFT\t\t16\n@@ -440,6 +446,7 @@\n #define ID_AA64PFR0_EL1_SHIFT\t\t4\n #define ID_AA64PFR0_EL0_SHIFT\t\t0\n \n+#define ID_AA64PFR0_SVE\t\t\t0x1\n #define ID_AA64PFR0_FP_NI\t\t0xf\n #define ID_AA64PFR0_FP_SUPPORTED\t0x0\n #define ID_AA64PFR0_ASIMD_NI\t\t0xf\n@@ -541,6 +548,20 @@\n #endif\n \n \n+/*\n+ * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which\n+ * are reserved by the SVE architecture for future expansion of the LEN\n+ * field, with compatible semantics.\n+ */\n+#define ZCR_ELx_LEN_SHIFT\t0\n+#define ZCR_ELx_LEN_SIZE\t9\n+#define ZCR_ELx_LEN_MASK\t0x1ff\n+\n+#define CPACR_EL1_ZEN_EL1EN\t(1 << 16) /* enable EL1 access */\n+#define CPACR_EL1_ZEN_EL0EN\t(1 << 17) /* enable EL0 access, if EL1EN set */\n+#define CPACR_EL1_ZEN\t\t(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)\n+\n+\n /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */\n #define SYS_MPIDR_SAFE_VAL\t\t(1UL << 31)\n \ndiff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c\nindex a1b7d64..20fbe42 100644\n--- a/arch/arm64/kernel/traps.c\n+++ b/arch/arm64/kernel/traps.c\n@@ -614,6 +614,7 @@ static const char *esr_class_str[] = {\n \t[ESR_ELx_EC_HVC64]\t\t= \"HVC (AArch64)\",\n \t[ESR_ELx_EC_SMC64]\t\t= \"SMC (AArch64)\",\n \t[ESR_ELx_EC_SYS64]\t\t= \"MSR/MRS (AArch64)\",\n+\t[ESR_ELx_EC_SVE]\t\t= \"SVE\",\n \t[ESR_ELx_EC_IMP_DEF]\t\t= \"EL3 IMP DEF\",\n \t[ESR_ELx_EC_IABT_LOW]\t\t= \"IABT (lower EL)\",\n \t[ESR_ELx_EC_IABT_CUR]\t\t= \"IABT (current EL)\",\n","prefixes":["v4","06/28"]}