{"id":831127,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831127/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20171027072612.26565-2-jeffy.chen@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171027072612.26565-2-jeffy.chen@rock-chips.com>","list_archive_url":null,"date":"2017-10-27T07:26:06","name":"[RFC,v10,1/7] dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"7ab6ad13d1e92c8710d15c1946df7cbc4da65e27","submitter":{"id":67754,"url":"http://patchwork.ozlabs.org/api/1.2/people/67754/?format=json","name":"Jeffy Chen","email":"jeffy.chen@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20171027072612.26565-2-jeffy.chen@rock-chips.com/mbox/","series":[{"id":10523,"url":"http://patchwork.ozlabs.org/api/1.2/series/10523/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=10523","date":"2017-10-27T07:26:06","name":"PCI: rockchip: Move PCIe WAKE# handling into pci core","version":10,"mbox":"http://patchwork.ozlabs.org/series/10523/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831127/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831127/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yNb6R1GJmz9t2x\n\tfor ;\n\tFri, 27 Oct 2017 18:26:55 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752077AbdJ0H0p (ORCPT );\n\tFri, 27 Oct 2017 03:26:45 -0400","from regular1.263xmail.com ([211.150.99.135]:52027 \"EHLO\n\tregular1.263xmail.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751068AbdJ0H0g (ORCPT\n\t); Fri, 27 Oct 2017 03:26:36 -0400","from jeffy.chen?rock-chips.com (unknown [192.168.167.192])\n\tby regular1.263xmail.com (Postfix) with ESMTP id C71501DEFB;\n\tFri, 27 Oct 2017 15:26:31 +0800 (CST)","from localhost (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 59CBE3CA;\n\tFri, 27 Oct 2017 15:26:25 +0800 (CST)","from localhost (unknown [103.29.142.67])\n\tby smtp.263.net (Postfix) whith ESMTP id 5803OVVLPZ;\n\tFri, 27 Oct 2017 15:26:31 +0800 (CST)"],"X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"jeffy.chen@rock-chips.com","X-FST-TO":"linux-kernel@vger.kernel.org","X-SENDER-IP":"103.29.142.67","X-LOGIN-NAME":"jeffy.chen@rock-chips.com","X-UNIQUE-TAG":"<1d7e5b5644698a0d2767f13fc92b8a4f>","X-ATTACHMENT-NUM":"0","X-SENDER":"cjf@rock-chips.com","X-DNS-TYPE":"0","From":"Jeffy Chen ","To":"linux-kernel@vger.kernel.org, bhelgaas@google.com","Cc":"linux-pm@vger.kernel.org, tony@atomide.com,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\trjw@rjwysocki.net, dianders@chromium.org,\n\tJeffy Chen ,\n\tdevicetree@vger.kernel.org, linux-pci@vger.kernel.org,\n\tRob Herring , Mark Rutland ","Subject":"[RFC PATCH v10 1/7] dt-bindings: PCI: Add definition of PCIe WAKE#\n\tirq and PCI irq","Date":"Fri, 27 Oct 2017 15:26:06 +0800","Message-Id":"<20171027072612.26565-2-jeffy.chen@rock-chips.com>","X-Mailer":"git-send-email 2.11.0","In-Reply-To":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>","References":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"We are going to handle PCIe WAKE# pin for PCI bus bridges and PCI\ndevices in the pci core, so add definitions of the optional PCIe\nWAKE# pin for PCI bus bridges and PCI devices.\n\nAlso add an definition of the optional PCI interrupt pin for PCI\ndevices to distinguish it from the PCIe WAKE# pin.\n\nSigned-off-by: Jeffy Chen \n---\n\nChanges in v10: None\nChanges in v9:\nAdd section for PCI devices and rewrite the commit message.\n\nChanges in v8:\nAdd optional \"pci\", and rewrite commit message.\n\nChanges in v7: None\nChanges in v6: None\nChanges in v5:\nMove to pci.txt\n\nChanges in v3: None\nChanges in v2: None\n\n Documentation/devicetree/bindings/pci/pci.txt | 8 ++++++++\n 1 file changed, 8 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt\nindex c77981c5dd18..d4406d4e15ad 100644\n--- a/Documentation/devicetree/bindings/pci/pci.txt\n+++ b/Documentation/devicetree/bindings/pci/pci.txt\n@@ -24,3 +24,11 @@ driver implementation may support the following properties:\n unsupported link speed, for instance, trying to do training for\n unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'\n for gen2, and '1' for gen1. Any other values are invalid.\n+- interrupts: Interrupt specifier for each name in interrupt-names.\n+- interrupt-names: May contains \"wakeup\" for PCIe WAKE# interrupt.\n+\n+PCI devices have standardized Device Tree bindings:\n+\n+- interrupts: Interrupt specifier for each name in interrupt-names.\n+- interrupt-names: May contains \"wakeup\" for PCIe WAKE# interrupt and \"pci\" for\n+ PCI interrupt.\n","prefixes":["RFC","v10","1/7"]}