{"id":831050,"url":"http://patchwork.ozlabs.org/api/1.2/patches/831050/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20171027040833.3644-9-aneesh.kumar@linux.vnet.ibm.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.2/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<20171027040833.3644-9-aneesh.kumar@linux.vnet.ibm.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/20171027040833.3644-9-aneesh.kumar@linux.vnet.ibm.com/","date":"2017-10-27T04:08:25","name":"[08/16] powerpc/mm/hash: Don't track hash pte slot number in linux page table.","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"6134ef7ed4a52ccb1b80bac8cfbc858504d83652","submitter":{"id":664,"url":"http://patchwork.ozlabs.org/api/1.2/people/664/?format=json","name":"Aneesh Kumar K.V","email":"aneesh.kumar@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20171027040833.3644-9-aneesh.kumar@linux.vnet.ibm.com/mbox/","series":[{"id":10486,"url":"http://patchwork.ozlabs.org/api/1.2/series/10486/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=10486","date":"2017-10-27T04:08:17","name":"Remove hash page table slot tracking from linux PTE","version":1,"mbox":"http://patchwork.ozlabs.org/series/10486/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/831050/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/831050/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNW0x1CdLz9t2d\n\tfor ;\n\tFri, 27 Oct 2017 15:21:53 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yNW0x0QmfzDrpk\n\tfor ;\n\tFri, 27 Oct 2017 15:21:53 +1100 (AEDT)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yNVkl2j76zDrcY\n\tfor ;\n\tFri, 27 Oct 2017 15:09:35 +1100 (AEDT)","from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv9R494sJ047526\n\tfor ; Fri, 27 Oct 2017 00:09:33 -0400","from e36.co.us.ibm.com (e36.co.us.ibm.com [32.97.110.154])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2dus55axvb-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Fri, 27 Oct 2017 00:09:32 -0400","from localhost\n\tby e36.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tThu, 26 Oct 2017 22:09:29 -0600","from b03ledav001.gho.boulder.ibm.com\n\t(b03ledav001.gho.boulder.ibm.com [9.17.130.232])\n\tby b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v9R49T0V9437450; Thu, 26 Oct 2017 21:09:29 -0700","from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id E3E7F6E176;\n\tThu, 26 Oct 2017 22:09:28 -0600 (MDT)","from skywalker.ibmmodules.com (unknown [9.85.199.61])\n\tby b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP id E0E206E175;\n\tThu, 26 Oct 2017 22:09:25 -0600 (MDT)"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=aneesh.kumar@linux.vnet.ibm.com; receiver=)","From":"\"Aneesh Kumar K.V\" ","To":"benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au","Subject":"[PATCH 08/16] powerpc/mm/hash: Don't track hash pte slot number in\n\tlinux page table.","Date":"Fri, 27 Oct 2017 09:38:25 +0530","X-Mailer":"git-send-email 2.13.6","In-Reply-To":"<20171027040833.3644-1-aneesh.kumar@linux.vnet.ibm.com>","References":"<20171027040833.3644-1-aneesh.kumar@linux.vnet.ibm.com>","X-TM-AS-GCONF":"00","x-cbid":"17102704-0020-0000-0000-00000CE87152","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007958; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000239; SDB=6.00937034; UDB=6.00472245;\n\tIPR=6.00717297; \n\tBA=6.00005660; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017735;\n\tXFM=3.00000015; UTC=2017-10-27 04:09:31","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17102704-0021-0000-0000-00005EAC0D4B","Message-Id":"<20171027040833.3644-9-aneesh.kumar@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-10-27_02:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tpriorityscore=1501\n\tmalwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0\n\tclxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0\n\tclassifier=spam adjust=0 reason=mlx scancount=1\n\tengine=8.0.1-1707230000\n\tdefinitions=main-1710270053","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org,\n\t\"Aneesh Kumar K.V\" ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"Now that we have updated all MMU hash operations to work with hash value instead\nof slot, remove slot tracking completely. We also remove real_pte because\nwithout slot tracking 4k, 64k and 64k subpages all have similar pte format.\n\nOne of the side effect of this is, we now don't track whether we have taken\na fault on 4k subpages on a 64k page config. That means a invalidate will try\nto invalidate all the 4k subpages.\n\nTo minimize the impact from above THP still track the slot details. With THP we\nhave 4096 subpages and we want to avoid calling invalidate on all. For THP we\ndon't track slot details as part of linux page table, but are tracked in the\ndeposited page table\n\nSigned-off-by: Aneesh Kumar K.V \n---\n arch/powerpc/include/asm/book3s/64/hash-4k.h | 16 +++-\n arch/powerpc/include/asm/book3s/64/hash-64k.h | 44 +---------\n arch/powerpc/include/asm/book3s/64/hash.h | 5 +-\n arch/powerpc/include/asm/book3s/64/pgtable.h | 26 ------\n arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 3 +-\n arch/powerpc/include/asm/pgtable-be-types.h | 10 ---\n arch/powerpc/include/asm/pgtable-types.h | 9 ---\n arch/powerpc/mm/dump_linuxpagetables.c | 10 ---\n arch/powerpc/mm/hash64_4k.c | 2 -\n arch/powerpc/mm/hash64_64k.c | 93 +++++-----------------\n arch/powerpc/mm/hash_native_64.c | 12 +--\n arch/powerpc/mm/hash_utils_64.c | 22 +----\n arch/powerpc/mm/hugetlbpage-hash64.c | 4 -\n arch/powerpc/mm/tlb_hash64.c | 9 +--\n arch/powerpc/platforms/pseries/lpar.c | 4 +-\n 15 files changed, 49 insertions(+), 220 deletions(-)","diff":"diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h\nindex 0c4e470571ca..d65dcb5826ff 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n@@ -17,8 +17,7 @@\n #define H_PGD_TABLE_SIZE\t(sizeof(pgd_t) << H_PGD_INDEX_SIZE)\n \n /* PTE flags to conserve for HPTE identification */\n-#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \\\n-\t\t\t H_PAGE_F_SECOND | H_PAGE_F_GIX)\n+#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE)\n /*\n * Not supported by 4k linux page size\n */\n@@ -27,6 +26,19 @@\n #define H_PAGE_COMBO\t0x0\n #define H_PTE_FRAG_NR\t0\n #define H_PTE_FRAG_SIZE_SHIFT 0\n+\n+#define pte_iterate_hashed_subpages(vpn, psize, index, shift)\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\tindex = 0;\t\t\t\t\t\t\\\n+\tshift = mmu_psize_defs[psize].shift;\t\t\t\\\n+\n+#define pte_iterate_hashed_end() } while(0)\n+/*\n+ * We expect this to be called only for user addresses or kernel virtual\n+ * addresses other than the linear mapping.\n+ */\n+#define pte_pagesize_index(mm, addr, pte)\tMMU_PAGE_4K\n+\n /*\n * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()\n */\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\nindex 9732837aaae8..ab36323b8a3e 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n@@ -25,8 +25,7 @@\n #define H_PAGE_COMBO_VALID\t(H_PAGE_F_GIX | H_PAGE_F_SECOND)\n \n /* PTE flags to conserve for HPTE identification */\n-#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_F_SECOND | \\\n-\t\t\t H_PAGE_F_GIX | H_PAGE_HASHPTE | H_PAGE_COMBO)\n+#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO)\n /*\n * we support 16 fragments per PTE page of 64K size.\n */\n@@ -40,55 +39,16 @@\n \n #ifndef __ASSEMBLY__\n #include \n-\n-/*\n- * With 64K pages on hash table, we have a special PTE format that\n- * uses a second \"half\" of the page table to encode sub-page information\n- * in order to deal with 64K made of 4K HW pages. Thus we override the\n- * generic accessors and iterators here\n- */\n-#define __real_pte __real_pte\n-static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)\n-{\n-\treal_pte_t rpte;\n-\tunsigned long *hidxp;\n-\n-\trpte.pte = pte;\n-\trpte.hidx = 0;\n-\tif (pte_val(pte) & H_PAGE_COMBO) {\n-\t\t/*\n-\t\t * Make sure we order the hidx load against the H_PAGE_COMBO\n-\t\t * check. The store side ordering is done in __hash_page_4K\n-\t\t */\n-\t\tsmp_rmb();\n-\t\thidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n-\t\trpte.hidx = *hidxp;\n-\t}\n-\treturn rpte;\n-}\n-\n-static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)\n-{\n-\tif ((pte_val(rpte.pte) & H_PAGE_COMBO))\n-\t\treturn (rpte.hidx >> (index<<2)) & 0xf;\n-\treturn (pte_val(rpte.pte) >> H_PAGE_F_GIX_SHIFT) & 0xf;\n-}\n-\n-#define __rpte_to_pte(r)\t((r).pte)\n-extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);\n /*\n * Trick: we set __end to va + 64k, which happens works for\n * a 16M page as well as we want only one iteration\n */\n-#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift)\t\\\n+#define pte_iterate_hashed_subpages(vpn, psize, index, shift)\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tunsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT));\t\\\n-\t\tunsigned __split = (psize == MMU_PAGE_4K ||\t\t\\\n-\t\t\t\t psize == MMU_PAGE_64K_AP);\t\t\\\n \t\tshift = mmu_psize_defs[psize].shift;\t\t\t\\\n \t\tfor (index = 0; vpn < __end; index++,\t\t\t\\\n \t\t\t vpn += (1L << (shift - VPN_SHIFT))) {\t\\\n-\t\t\tif (!__split || __rpte_sub_valid(rpte, index))\t\\\n \t\t\t\tdo {\n \n #define pte_iterate_hashed_end() } while(0); } } while(0)\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h\nindex f88452019114..d95a3d41d8d0 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash.h\n@@ -8,11 +8,8 @@\n *\n */\n #define H_PTE_NONE_MASK\t\t_PAGE_HPTEFLAGS\n-#define H_PAGE_F_GIX_SHIFT\t56\n #define H_PAGE_BUSY\t\t_RPAGE_RSV1 /* software: PTE & hash are busy */\n-#define H_PAGE_F_SECOND\t\t_RPAGE_RSV2\t/* HPTE is in 2ndary HPTEG */\n-#define H_PAGE_F_GIX\t\t(_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)\n-#define H_PAGE_HASHPTE\t\t_RPAGE_RPN43\t/* PTE has associated HPTE */\n+#define H_PAGE_HASHPTE\t\t_RPAGE_RSV2\t/* PTE has associated HPTE */\n \n #ifdef CONFIG_PPC_64K_PAGES\n #include \ndiff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h\nindex b9aff515b4de..9c2ffaaa5b80 100644\n--- a/arch/powerpc/include/asm/book3s/64/pgtable.h\n+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h\n@@ -316,32 +316,6 @@ extern unsigned long pci_io_base;\n \n #ifndef __ASSEMBLY__\n \n-/*\n- * This is the default implementation of various PTE accessors, it's\n- * used in all cases except Book3S with 64K pages where we have a\n- * concept of sub-pages\n- */\n-#ifndef __real_pte\n-\n-#define __real_pte(e,p)\t\t((real_pte_t){(e)})\n-#define __rpte_to_pte(r)\t((r).pte)\n-#define __rpte_to_hidx(r,index)\t(pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)\n-\n-#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \\\n-\tdo {\t\t\t\t\t\t\t \\\n-\t\tindex = 0;\t\t\t\t\t \\\n-\t\tshift = mmu_psize_defs[psize].shift;\t\t \\\n-\n-#define pte_iterate_hashed_end() } while(0)\n-\n-/*\n- * We expect this to be called only for user addresses or kernel virtual\n- * addresses other than the linear mapping.\n- */\n-#define pte_pagesize_index(mm, addr, pte)\tMMU_PAGE_4K\n-\n-#endif /* __real_pte */\n-\n static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,\n \t\t\t\t pte_t *ptep, unsigned long clr,\n \t\t\t\t unsigned long set, int huge)\ndiff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h\nindex 99c99bb04353..6fd4b5682056 100644\n--- a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h\n@@ -14,7 +14,6 @@ struct ppc64_tlb_batch {\n \tint\t\t\tactive;\n \tunsigned long\t\tindex;\n \tstruct mm_struct\t*mm;\n-\treal_pte_t\t\tpte[PPC64_TLB_BATCH_NR];\n \tunsigned long\t\tvpn[PPC64_TLB_BATCH_NR];\n \tunsigned int\t\tpsize;\n \tint\t\t\tssize;\n@@ -51,7 +50,7 @@ static inline void arch_leave_lazy_mmu_mode(void)\n #define arch_flush_lazy_mmu_mode() do {} while (0)\n \n \n-extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,\n+extern void flush_hash_page(unsigned long vpn, int psize,\n \t\t\t int ssize, unsigned long flags);\n extern void flush_hash_range(unsigned long number, int local);\n extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,\ndiff --git a/arch/powerpc/include/asm/pgtable-be-types.h b/arch/powerpc/include/asm/pgtable-be-types.h\nindex 67e7e3d990f4..367a6662e05e 100644\n--- a/arch/powerpc/include/asm/pgtable-be-types.h\n+++ b/arch/powerpc/include/asm/pgtable-be-types.h\n@@ -72,16 +72,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;\n #define pgprot_val(x)\t((x).pgprot)\n #define __pgprot(x)\t((pgprot_t) { (x) })\n \n-/*\n- * With hash config 64k pages additionally define a bigger \"real PTE\" type that\n- * gathers the \"second half\" part of the PTE for pseudo 64k pages\n- */\n-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)\n-typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;\n-#else\n-typedef struct { pte_t pte; } real_pte_t;\n-#endif\n-\n static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new)\n {\n \tunsigned long *p = (unsigned long *)ptep;\ndiff --git a/arch/powerpc/include/asm/pgtable-types.h b/arch/powerpc/include/asm/pgtable-types.h\nindex 369a164b545c..baa49eccff20 100644\n--- a/arch/powerpc/include/asm/pgtable-types.h\n+++ b/arch/powerpc/include/asm/pgtable-types.h\n@@ -45,15 +45,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;\n #define pgprot_val(x)\t((x).pgprot)\n #define __pgprot(x)\t((pgprot_t) { (x) })\n \n-/*\n- * With hash config 64k pages additionally define a bigger \"real PTE\" type that\n- * gathers the \"second half\" part of the PTE for pseudo 64k pages\n- */\n-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)\n-typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;\n-#else\n-typedef struct { pte_t pte; } real_pte_t;\n-#endif\n \n #ifdef CONFIG_PPC_STD_MMU_64\n #include \ndiff --git a/arch/powerpc/mm/dump_linuxpagetables.c b/arch/powerpc/mm/dump_linuxpagetables.c\nindex c9282d27b203..af98ad112c56 100644\n--- a/arch/powerpc/mm/dump_linuxpagetables.c\n+++ b/arch/powerpc/mm/dump_linuxpagetables.c\n@@ -214,16 +214,6 @@ static const struct flag_info flag_array[] = {\n \t\t.set\t= \"4K_pfn\",\n \t}, {\n #endif\n-\t\t.mask\t= H_PAGE_F_GIX,\n-\t\t.val\t= H_PAGE_F_GIX,\n-\t\t.set\t= \"f_gix\",\n-\t\t.is_val\t= true,\n-\t\t.shift\t= H_PAGE_F_GIX_SHIFT,\n-\t}, {\n-\t\t.mask\t= H_PAGE_F_SECOND,\n-\t\t.val\t= H_PAGE_F_SECOND,\n-\t\t.set\t= \"f_second\",\n-\t}, {\n #endif\n \t\t.mask\t= _PAGE_SPECIAL,\n \t\t.val\t= _PAGE_SPECIAL,\ndiff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c\nindex afb79100f0ce..68ae99ea6bcf 100644\n--- a/arch/powerpc/mm/hash64_4k.c\n+++ b/arch/powerpc/mm/hash64_4k.c\n@@ -113,8 +113,6 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t\treturn -1;\n \t\t}\n \t\tnew_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;\n-\t\tnew_pte |= (slot << H_PAGE_F_GIX_SHIFT) &\n-\t\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n \t}\n \t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \treturn 0;\ndiff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c\nindex 096fdfaf6f1c..3beb3063202f 100644\n--- a/arch/powerpc/mm/hash64_64k.c\n+++ b/arch/powerpc/mm/hash64_64k.c\n@@ -15,42 +15,12 @@\n #include \n #include \n #include \n-/*\n- * index from 0 - 15\n- */\n-bool __rpte_sub_valid(real_pte_t rpte, unsigned long index)\n-{\n-\tunsigned long g_idx;\n-\tunsigned long ptev = pte_val(rpte.pte);\n-\n-\tg_idx = (ptev & H_PAGE_COMBO_VALID) >> H_PAGE_F_GIX_SHIFT;\n-\tindex = index >> 2;\n-\tif (g_idx & (0x1 << index))\n-\t\treturn true;\n-\telse\n-\t\treturn false;\n-}\n-/*\n- * index from 0 - 15\n- */\n-static unsigned long mark_subptegroup_valid(unsigned long ptev, unsigned long index)\n-{\n-\tunsigned long g_idx;\n-\n-\tif (!(ptev & H_PAGE_COMBO))\n-\t\treturn ptev;\n-\tindex = index >> 2;\n-\tg_idx = 0x1 << index;\n-\n-\treturn ptev | (g_idx << H_PAGE_F_GIX_SHIFT);\n-}\n \n int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t pte_t *ptep, unsigned long trap, unsigned long flags,\n \t\t int ssize, int subpg_prot)\n {\n-\treal_pte_t rpte;\n-\tunsigned long *hidxp;\n+\tint ret;\n \tunsigned long hpte_group;\n \tunsigned int subpg_index;\n \tunsigned long rflags, pa;\n@@ -99,7 +69,6 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \n \tsubpg_index = (ea & (PAGE_SIZE - 1)) >> shift;\n \tvpn = hpt_vpn(ea, vsid, ssize);\n-\trpte = __real_pte(__pte(old_pte), ptep);\n \t/*\n \t *None of the sub 4k page is hashed\n \t */\n@@ -110,37 +79,31 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t * as a 64k HW page, and invalidate the 64k HPTE if so.\n \t */\n \tif (!(old_pte & H_PAGE_COMBO)) {\n-\t\tflush_hash_page(vpn, rpte, MMU_PAGE_64K, ssize, flags);\n-\t\t/*\n-\t\t * clear the old slot details from the old and new pte.\n-\t\t * On hash insert failure we use old pte value and we don't\n-\t\t * want slot information there if we have a insert failure.\n-\t\t */\n-\t\told_pte &= ~(H_PAGE_HASHPTE | H_PAGE_F_GIX | H_PAGE_F_SECOND);\n-\t\tnew_pte &= ~(H_PAGE_HASHPTE | H_PAGE_F_GIX | H_PAGE_F_SECOND);\n+\t\tflush_hash_page(vpn, MMU_PAGE_64K, ssize, flags);\n+\t\told_pte &= ~H_PAGE_HASHPTE;\n+\t\tnew_pte &= ~H_PAGE_HASHPTE;\n \t\tgoto htab_insert_hpte;\n \t}\n \t/*\n-\t * Check for sub page valid and update\n+\t * We are not tracking the validty of 4k entries seperately. Hence\n+\t * If H_PAGE_HASHPTE is set, we always try an update.\n \t */\n-\tif (__rpte_sub_valid(rpte, subpg_index)) {\n-\t\tint ret;\n-\n-\t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tret = mmu_hash_ops.hash_updatepp(hash, rflags, vpn,\n-\t\t\t\t\t\t MMU_PAGE_4K, MMU_PAGE_4K,\n-\t\t\t\t\t\t ssize, flags);\n-\t\t/*\n-\t\t * if we failed because typically the HPTE wasn't really here\n-\t\t * we try an insertion.\n-\t\t */\n-\t\tif (ret == -1)\n-\t\t\tgoto htab_insert_hpte;\n-\n+\thash = hpt_hash(vpn, shift, ssize);\n+\tret = mmu_hash_ops.hash_updatepp(hash, rflags, vpn,\n+\t\t\t\t\t MMU_PAGE_4K, MMU_PAGE_4K,\n+\t\t\t\t\t ssize, flags);\n+\t/*\n+\t * if we failed because typically the HPTE wasn't really here\n+\t * we try an insertion.\n+\t */\n+\tif (ret != -1) {\n \t\t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \t\treturn 0;\n \t}\n-\n+\t/*\n+\t * updatepp failed, hash table doesn't have an entry for this,\n+\t * insert a new entry\n+\t */\n htab_insert_hpte:\n \t/*\n \t * handle H_PAGE_4K_PFN case\n@@ -192,21 +155,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t\t\t MMU_PAGE_4K, MMU_PAGE_4K, old_pte);\n \t\treturn -1;\n \t}\n-\t/*\n-\t * Insert slot number & secondary bit in PTE second half,\n-\t * clear H_PAGE_BUSY and set appropriate HPTE slot bit\n-\t * Since we have H_PAGE_BUSY set on ptep, we can be sure\n-\t * nobody is undating hidx.\n-\t */\n-\thidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n-\trpte.hidx &= ~(0xfUL << (subpg_index << 2));\n-\t*hidxp = rpte.hidx | (slot << (subpg_index << 2));\n-\tnew_pte = mark_subptegroup_valid(new_pte, subpg_index);\n \tnew_pte |= H_PAGE_HASHPTE;\n-\t/*\n-\t * check __real_pte for details on matching smp_rmb()\n-\t */\n-\tsmp_wmb();\n \t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \treturn 0;\n }\n@@ -311,9 +260,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,\n \t\t\t\t\t MMU_PAGE_64K, MMU_PAGE_64K, old_pte);\n \t\t\treturn -1;\n \t\t}\n-\t\tnew_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;\n-\t\tnew_pte |= (slot << H_PAGE_F_GIX_SHIFT) &\n-\t\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n+\t\tnew_pte = new_pte | H_PAGE_HASHPTE;\n \t}\n \t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \treturn 0;\ndiff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c\nindex 3b061844929c..a268d3a62425 100644\n--- a/arch/powerpc/mm/hash_native_64.c\n+++ b/arch/powerpc/mm/hash_native_64.c\n@@ -746,7 +746,6 @@ static void native_flush_hash_range(unsigned long number, int local)\n \tunsigned long hash, index, shift;\n \tstruct hash_pte *hptep;\n \tunsigned long flags;\n-\treal_pte_t pte;\n \tstruct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);\n \tunsigned long psize = batch->psize;\n \tint ssize = batch->ssize;\n@@ -760,9 +759,8 @@ static void native_flush_hash_range(unsigned long number, int local)\n \n \tfor (i = 0; i < number; i++) {\n \t\tvpn = batch->vpn[i];\n-\t\tpte = batch->pte[i];\n \n-\t\tpte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {\n+\t\tpte_iterate_hashed_subpages(vpn, psize, index, shift) {\n \t\t\thash = hpt_hash(vpn, shift, ssize);\n \t\t\thptep = native_hpte_find(hash, vpn, psize, ssize);\n \t\t\tif (!hptep)\n@@ -778,10 +776,8 @@ static void native_flush_hash_range(unsigned long number, int local)\n \t\tasm volatile(\"ptesync\":::\"memory\");\n \t\tfor (i = 0; i < number; i++) {\n \t\t\tvpn = batch->vpn[i];\n-\t\t\tpte = batch->pte[i];\n \n-\t\t\tpte_iterate_hashed_subpages(pte, psize,\n-\t\t\t\t\t\t vpn, index, shift) {\n+\t\t\tpte_iterate_hashed_subpages(vpn, psize, index, shift) {\n \t\t\t\t__tlbiel(vpn, psize, psize, ssize);\n \t\t\t} pte_iterate_hashed_end();\n \t\t}\n@@ -795,10 +791,8 @@ static void native_flush_hash_range(unsigned long number, int local)\n \t\tasm volatile(\"ptesync\":::\"memory\");\n \t\tfor (i = 0; i < number; i++) {\n \t\t\tvpn = batch->vpn[i];\n-\t\t\tpte = batch->pte[i];\n \n-\t\t\tpte_iterate_hashed_subpages(pte, psize,\n-\t\t\t\t\t\t vpn, index, shift) {\n+\t\t\tpte_iterate_hashed_subpages(vpn, psize, index, shift) {\n \t\t\t\t__tlbie(vpn, psize, psize, ssize);\n \t\t\t} pte_iterate_hashed_end();\n \t\t}\ndiff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\nindex 8635b241e2d5..e700660459c4 100644\n--- a/arch/powerpc/mm/hash_utils_64.c\n+++ b/arch/powerpc/mm/hash_utils_64.c\n@@ -974,21 +974,8 @@ void __init hash__early_init_devtree(void)\n \n void __init hash__early_init_mmu(void)\n {\n-\t/*\n-\t * We have code in __hash_page_64K() and elsewhere, which assumes it can\n-\t * do the following:\n-\t * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);\n-\t *\n-\t * Where the slot number is between 0-15, and values of 8-15 indicate\n-\t * the secondary bucket. For that code to work H_PAGE_F_SECOND and\n-\t * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and\n-\t * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here\n-\t * with a BUILD_BUG_ON().\n-\t */\n-\tBUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));\n \n \thtab_init_page_sizes();\n-\n \t/*\n \t * initialize page table size\n \t */\n@@ -1590,14 +1577,13 @@ static inline void tm_flush_hash_page(int local)\n /* WARNING: This is called from hash_low_64.S, if you change this prototype,\n * do not forget to update the assembly call site !\n */\n-void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,\n-\t\t unsigned long flags)\n+void flush_hash_page(unsigned long vpn, int psize, int ssize, unsigned long flags)\n {\n \tunsigned long hash, index, shift;\n \tint local = flags & HPTE_LOCAL_UPDATE;\n \n \tDBG_LOW(\"flush_hash_page(vpn=%016lx)\\n\", vpn);\n-\tpte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {\n+\tpte_iterate_hashed_subpages(vpn, psize, index, shift) {\n \t\thash = hpt_hash(vpn, shift, ssize);\n \t\tDBG_LOW(\" sub %ld: hash=%lx\\n\", index, hash);\n \t\t/*\n@@ -1679,8 +1665,8 @@ void flush_hash_range(unsigned long number, int local)\n \t\t\tthis_cpu_ptr(&ppc64_tlb_batch);\n \n \t\tfor (i = 0; i < number; i++)\n-\t\t\tflush_hash_page(batch->vpn[i], batch->pte[i],\n-\t\t\t\t\tbatch->psize, batch->ssize, local);\n+\t\t\tflush_hash_page(batch->vpn[i], batch->psize,\n+\t\t\t\t\tbatch->ssize, local);\n \t}\n }\n \ndiff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c\nindex 4eb8c9d2f452..8aff8d17d91c 100644\n--- a/arch/powerpc/mm/hugetlbpage-hash64.c\n+++ b/arch/powerpc/mm/hugetlbpage-hash64.c\n@@ -100,11 +100,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t\t\t\t mmu_psize, mmu_psize, old_pte);\n \t\t\treturn -1;\n \t\t}\n-\n-\t\tnew_pte |= (slot << H_PAGE_F_GIX_SHIFT) &\n-\t\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n \t}\n-\n \t/*\n \t * No need to use ldarx/stdcx here\n \t */\ndiff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c\nindex 881ebd53ffc2..39ebb0bf4694 100644\n--- a/arch/powerpc/mm/tlb_hash64.c\n+++ b/arch/powerpc/mm/tlb_hash64.c\n@@ -50,7 +50,6 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,\n \tunsigned long vsid;\n \tunsigned int psize;\n \tint ssize;\n-\treal_pte_t rpte;\n \tint i;\n \n \ti = batch->index;\n@@ -91,14 +90,13 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,\n \t}\n \tWARN_ON(vsid == 0);\n \tvpn = hpt_vpn(addr, vsid, ssize);\n-\trpte = __real_pte(__pte(pte), ptep);\n \n \t/*\n \t * Check if we have an active batch on this CPU. If not, just\n \t * flush now and return.\n \t */\n \tif (!batch->active) {\n-\t\tflush_hash_page(vpn, rpte, psize, ssize, mm_is_thread_local(mm));\n+\t\tflush_hash_page(vpn, psize, ssize, mm_is_thread_local(mm));\n \t\tput_cpu_var(ppc64_tlb_batch);\n \t\treturn;\n \t}\n@@ -123,7 +121,6 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,\n \t\tbatch->psize = psize;\n \t\tbatch->ssize = ssize;\n \t}\n-\tbatch->pte[i] = rpte;\n \tbatch->vpn[i] = vpn;\n \tbatch->index = ++i;\n \tif (i >= PPC64_TLB_BATCH_NR)\n@@ -145,8 +142,8 @@ void __flush_tlb_pending(struct ppc64_tlb_batch *batch)\n \ti = batch->index;\n \tlocal = mm_is_thread_local(batch->mm);\n \tif (i == 1)\n-\t\tflush_hash_page(batch->vpn[0], batch->pte[0],\n-\t\t\t\tbatch->psize, batch->ssize, local);\n+\t\tflush_hash_page(batch->vpn[0], batch->psize,\n+\t\t\t\tbatch->ssize, local);\n \telse\n \t\tflush_hash_range(i, local);\n \tbatch->index = 0;\ndiff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c\nindex 511a2e9ed9a0..52d2e3038c05 100644\n--- a/arch/powerpc/platforms/pseries/lpar.c\n+++ b/arch/powerpc/platforms/pseries/lpar.c\n@@ -616,7 +616,6 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)\n \tint lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);\n \tunsigned long param[PLPAR_HCALL9_BUFSIZE];\n \tunsigned long index, shift;\n-\treal_pte_t pte;\n \tint psize, ssize, pix;\n \n \tif (lock_tlbie)\n@@ -627,8 +626,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)\n \tpix = 0;\n \tfor (i = 0; i < number; i++) {\n \t\tvpn = batch->vpn[i];\n-\t\tpte = batch->pte[i];\n-\t\tpte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {\n+\t\tpte_iterate_hashed_subpages(vpn, psize, index, shift) {\n \t\t\tlong slot;\n \n \t\t\tslot = pSeries_lpar_hpte_find(vpn, psize, ssize);\n","prefixes":["08/16"]}