{"id":829982,"url":"http://patchwork.ozlabs.org/api/1.2/patches/829982/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20171024175714.15840-3-clabbe.montjoie@gmail.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/1.2/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20171024175714.15840-3-clabbe.montjoie@gmail.com>","list_archive_url":null,"date":"2017-10-24T17:57:06","name":"[v9,02/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"2002db08757ed84f92dfb5c6652c00815d5fbcac","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/1.2/people/64152/?format=json","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/1.2/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20171024175714.15840-3-clabbe.montjoie@gmail.com/mbox/","series":[{"id":10031,"url":"http://patchwork.ozlabs.org/api/1.2/series/10031/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=10031","date":"2017-10-24T17:57:06","name":"net: stmmac: dwmac-sun8i: Handle integrated PHY","version":9,"mbox":"http://patchwork.ozlabs.org/series/10031/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/829982/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/829982/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"j756uIbJ\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yM1KM1lLkz9sRg\n\tfor ;\n\tWed, 25 Oct 2017 05:00:55 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751812AbdJXSAv (ORCPT );\n\tTue, 24 Oct 2017 14:00:51 -0400","from mail-wm0-f65.google.com ([74.125.82.65]:55585 \"EHLO\n\tmail-wm0-f65.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751550AbdJXSAr (ORCPT\n\t); Tue, 24 Oct 2017 14:00:47 -0400","by mail-wm0-f65.google.com with SMTP id u138so18003014wmu.4;\n\tTue, 24 Oct 2017 11:00:46 -0700 (PDT)","from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr.\n\t[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id\n\ts18sm818968wrg.87.2017.10.24.11.00.44\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 24 Oct 2017 11:00:45 -0700 (PDT)"],"DKIM-Signature":"v=1; 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See phy.txt for the generic PHY bindings.\n \n-Required properties of the phy node with the following compatibles:\n+The following compatibles require that the emac node have a mdio-mux child\n+node called \"mdio-mux\":\n+ - \"allwinner,sun8i-h3-emac\"\n+ - \"allwinner,sun8i-v3s-emac\":\n+Required properties for the mdio-mux node:\n+ - compatible = \"allwinner,sun8i-h3-mdio-mux\"\n+ - mdio-parent-bus: a phandle to EMAC mdio\n+ - one child mdio for the integrated mdio with the compatible\n+ \"allwinner,sun8i-h3-mdio-internal\"\n+ - one child mdio for the external mdio if present (V3s have none)\n+Required properties for the mdio-mux children node:\n+ - reg: 1 for internal MDIO bus, 2 for external MDIO bus\n+\n+The following compatibles require a PHY node representing the integrated\n+PHY, under the integrated MDIO bus node if an mdio-mux node is used:\n - \"allwinner,sun8i-h3-emac\",\n - \"allwinner,sun8i-v3s-emac\":\n+\n+Additional information regarding generic multiplexer properties can be found\n+at Documentation/devicetree/bindings/net/mdio-mux.txt\n+\n+Required properties of the integrated phy node:\n - clocks: a phandle to the reference clock for the EPHY\n - resets: a phandle to the reset control for the EPHY\n+- Must be a child of the integrated mdio\n \n-Example:\n-\n+Example with integrated PHY:\n emac: ethernet@1c0b000 {\n \tcompatible = \"allwinner,sun8i-h3-emac\";\n \tsyscon = <&syscon>;\n@@ -72,13 +91,115 @@ emac: ethernet@1c0b000 {\n \tphy-handle = <&int_mii_phy>;\n \tphy-mode = \"mii\";\n \tallwinner,leds-active-low;\n+\n+\tmdio0: mdio {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t};\n+\n+\tmdio-mux {\n+\t\tcompatible = \"mdio-mux\", \"allwinner,sun8i-h3-mdio-mux\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tmdio-parent-bus = <&mdio0>;\n+\n+\t\tint_mdio: mdio@1 {\n+\t\t\tcompatible = \"allwinner,sun8i-h3-mdio-internal\";\n+\t\t\treg = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tint_mii_phy: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n+\t\t\t\tresets = <&ccu RST_BUS_EPHY>;\n+\t\t\t\tphy-is-integrated;\n+\t\t\t};\n+\t\t};\n+\t\text_mdio: mdio@2 {\n+\t\t\treg = <2>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\t};\n+};\n+\n+Example with external PHY:\n+emac: ethernet@1c0b000 {\n+\tcompatible = \"allwinner,sun8i-h3-emac\";\n+\tsyscon = <&syscon>;\n+\treg = <0x01c0b000 0x104>;\n+\tinterrupts = ;\n+\tinterrupt-names = \"macirq\";\n+\tresets = <&ccu RST_BUS_EMAC>;\n+\treset-names = \"stmmaceth\";\n+\tclocks = <&ccu CLK_BUS_EMAC>;\n+\tclock-names = \"stmmaceth\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii\";\n+\tallwinner,leds-active-low;\n+\n+\tmdio0: mdio {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t};\n+\n+\tmdio-mux {\n+\t\tcompatible = \"mdio-mux\", \"allwinner,sun8i-h3-mdio-mux\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tmdio-parent-bus = <&mdio0>;\n+\n+\t\tint_mdio: mdio@1 {\n+\t\t\tcompatible = \"allwinner,sun8i-h3-mdio-internal\";\n+\t\t\treg = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tint_mii_phy: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n+\t\t\t\tresets = <&ccu RST_BUS_EPHY>;\n+\t\t\t};\n+\t\t};\n+\t\text_mdio: mdio@2 {\n+\t\t\treg = <2>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\text_rgmii_phy: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\t\t}:\n+\t};\n+};\n+\n+Example with SoC without integrated PHY\n+\n+emac: ethernet@1c0b000 {\n+\tcompatible = \"allwinner,sun8i-a83t-emac\";\n+\tsyscon = <&syscon>;\n+\treg = <0x01c0b000 0x104>;\n+\tinterrupts = ;\n+\tinterrupt-names = \"macirq\";\n+\tresets = <&ccu RST_BUS_EMAC>;\n+\treset-names = \"stmmaceth\";\n+\tclocks = <&ccu CLK_BUS_EMAC>;\n+\tclock-names = \"stmmaceth\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii\";\n+\n \tmdio: mdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n-\t\tint_mii_phy: ethernet-phy@1 {\n+\t\text_rgmii_phy: ethernet-phy@1 {\n \t\t\treg = <1>;\n-\t\t\tclocks = <&ccu CLK_BUS_EPHY>;\n-\t\t\tresets = <&ccu RST_BUS_EPHY>;\n \t\t};\n \t};\n };\n","prefixes":["v9","02/10"]}