{"id":816174,"url":"http://patchwork.ozlabs.org/api/1.2/patches/816174/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/patch/1505909388-13513-1-git-send-email-Dave.Martin@arm.com/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/1.2/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505909388-13513-1-git-send-email-Dave.Martin@arm.com>","list_archive_url":null,"date":"2017-09-20T12:09:48","name":"[v2] bootwrapper: SVE: Enable SVE for EL2 and below","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8a58c6bfe44c44032026a6847a79266aee64b30d","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.2/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-imx/patch/1505909388-13513-1-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":4096,"url":"http://patchwork.ozlabs.org/api/1.2/series/4096/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=4096","date":"2017-09-20T12:09:48","name":"[v2] bootwrapper: SVE: Enable SVE for EL2 and below","version":2,"mbox":"http://patchwork.ozlabs.org/series/4096/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816174/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816174/checks/","tags":{},"related":[],"headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"NZCwLwlb\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxz8q0DDjz9t2Q\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 22:10:34 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dudpk-0004H0-AJ; Wed, 20 Sep 2017 12:10:28 +0000","from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dudpb-0002yC-U6 for linux-arm-kernel@lists.infradead.org;\n\tWed, 20 Sep 2017 12:10:26 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5B8A280D;\n\tWed, 20 Sep 2017 05:09:59 -0700 (PDT)","from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t8F6253F578; Wed, 20 Sep 2017 05:09:58 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To\n\t:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=LTocRSNPcBtp+5wTUjTZ2dElV1K/Dl3HMn/wAQtaORs=;\n\tb=NZCwLwlbQDoLcz\n\tORag/M1mCn1X6RE9hej19SR/A0oGnTclzuEKEq9wyad/AN+1zCHkbTIelCi6oeOU76NGr9NudItpN\n\tZdO603XzUp8yDtCkot6FkHMvtcqJqXpNuibozGFYupOFQdqtSBP66mGL2AGwvlLM3KbCg7ID62N37\n\tgCr0zdL0m5PYtHKvNSN3eCcyfCE48j5+vX9CDiuaSl4nbVcfhoaqezXtadp3clWqzcZZfBXp+8cSP\n\tfLC2Ed6esZZQjkjM997DrcDIJ6wqFnp4Mr+o8HYsh3jXI5t9WR2xdUh1yJx0dJwmQNzQF3uf4cYBy\n\tbJ7OdciFf4hiBIXu1t/w==;","From":"Dave Martin <Dave.Martin@arm.com>","To":"linux-arm-kernel@lists.infradead.org","Subject":"[PATCH v2] bootwrapper: SVE: Enable SVE for EL2 and below","Date":"Wed, 20 Sep 2017 13:09:48 +0100","Message-Id":"<1505909388-13513-1-git-send-email-Dave.Martin@arm.com>","X-Mailer":"git-send-email 2.1.4","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170920_051020_010088_36F8BB5E ","X-CRM114-Status":"UNSURE (   8.21  )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-6.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"Mark Rutland <mark.rutland@arm.com>, =?utf-8?q?Alex_Benn=C3=A9e?=\n\t<alex.bennee@linaro.org>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"By default, SVE will trap to EL3.  We also want to make sure that\nlower ELs have access to the full SVE vector length before dropping\ndown.\n\nThis patch programs CPTR_EL3 and ZCR_EL3 appropriately to enable\nSVE for lower exception levels and make sure that they can use the\nfull vector length provided by the hardware.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: Alex Bennée <alex.bennee@linaro.org>\n---\n\nThis is basically the same as v1 [1], but rebased to an up-to-date\nbootwrapper tree.  (I was previously tracking Catalin's tree, which no\nlonger exists...)\n\n[1] [PATCH] bootwrapper: SVE: Enable SVE for EL2 and below\nhttp://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/527000.html\n\n\n arch/aarch64/boot.S            | 13 +++++++++++++\n arch/aarch64/include/asm/cpu.h |  5 +++++\n 2 files changed, 18 insertions(+)","diff":"diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S\nindex ceeee76..f7d795a 100644\n--- a/arch/aarch64/boot.S\n+++ b/arch/aarch64/boot.S\n@@ -45,6 +45,19 @@ _start:\n \n \tmsr\tcptr_el3, xzr\t\t\t// Disable copro. traps to EL3\n \n+\tmrs\tx0, id_aa64pfr0_el1\n+\tubfx\tx0, x0, #32, #4\t\t\t// SVE present?\n+\tcbz\tx0, 1f\t\t\t\t// Skip SVE init if not\n+\n+\tmrs\tx0, cptr_el3\n+\torr\tx0, x0, #CPTR_EL3_EZ\t\t// enable SVE\n+\tmsr\tcptr_el3, x0\n+\tisb\n+\n+\tmov\tx0, #ZCR_EL3_LEN_MASK\t\t// SVE: Enable full vector len\n+\tmsr\tZCR_EL3, x0\t\t\t// for EL2.\n+\n+1:\n \tldr\tx0, =CNTFRQ\n \tmsr\tcntfrq_el0, x0\n \ndiff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h\nindex 66726ef..ccb5397 100644\n--- a/arch/aarch64/include/asm/cpu.h\n+++ b/arch/aarch64/include/asm/cpu.h\n@@ -27,6 +27,11 @@\n #define SPSR_EL2H\t\t(9 << 0)\t/* EL2 Handler mode */\n #define SPSR_HYP\t\t(0x1a << 0)\t/* M[3:0] = hyp, M[4] = AArch32 */\n \n+#define CPTR_EL3_EZ\t\t(1 << 8)\n+\n+#define ZCR_EL3\t\t\ts3_6_c1_c2_0\n+#define ZCR_EL3_LEN_MASK\t0x1ff\n+\n #define SCTLR_EL1_CP15BEN\t(1 << 5)\n #define SCTLR_EL1_RES1\t\t(3 << 28 | 3 << 22 | 1 << 11)\n \n","prefixes":["v2"]}