{"id":814809,"url":"http://patchwork.ozlabs.org/api/1.2/patches/814809/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1d61ec4d-da94-e96a-e1f6-509a4e80daec@siemens.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1d61ec4d-da94-e96a-e1f6-509a4e80daec@siemens.com>","list_archive_url":null,"date":"2017-09-18T07:51:27","name":"arm: Fix SMC reporting to EL2 when QEMU provides PSCI","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bbe6e1f8194099857ee03f669af93d1cb2f9083b","submitter":{"id":710,"url":"http://patchwork.ozlabs.org/api/1.2/people/710/?format=json","name":"Jan Kiszka","email":"jan.kiszka@siemens.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1d61ec4d-da94-e96a-e1f6-509a4e80daec@siemens.com/mbox/","series":[{"id":3578,"url":"http://patchwork.ozlabs.org/api/1.2/series/3578/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3578","date":"2017-09-18T07:51:27","name":"arm: Fix SMC reporting to EL2 when QEMU provides PSCI","version":1,"mbox":"http://patchwork.ozlabs.org/series/3578/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814809/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814809/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwdXX1bscz9s3w\n\tfor ;\n\tMon, 18 Sep 2017 17:52:59 +1000 (AEST)","from localhost ([::1]:35122 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtqrS-0005Et-4d\n\tfor incoming@patchwork.ozlabs.org; Mon, 18 Sep 2017 03:52:58 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:60247)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dtqq5-0004S6-6l\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 03:51:34 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dtqq2-0002xJ-4M\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 03:51:33 -0400","from goliath.siemens.de ([192.35.17.28]:50714)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dtqq1-0002wq-PT\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 03:51:30 -0400","from mail1.siemens.de (mail1.siemens.de [139.23.33.14])\n\tby goliath.siemens.de (8.15.2/8.15.2) with ESMTPS id v8I7pS3q028395\n\t(version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n\tMon, 18 Sep 2017 09:51:28 +0200","from md1f2u6c.ww002.siemens.net ([139.22.134.132])\n\tby mail1.siemens.de (8.15.2/8.15.2) with ESMTP id v8I7pRHR032566;\n\tMon, 18 Sep 2017 09:51:27 +0200"],"To":"Peter Maydell ,\n\tqemu-devel ","From":"Jan Kiszka ","Message-ID":"<1d61ec4d-da94-e96a-e1f6-509a4e80daec@siemens.com>","Date":"Mon, 18 Sep 2017 09:51:27 +0200","User-Agent":"Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12)\n\tGecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12\n\tMnenhy/0.7.5.666","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"192.35.17.28","Subject":"[Qemu-devel] [PATCH] arm: Fix SMC reporting to EL2 when QEMU\n\tprovides PSCI","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Jan Kiszka \n\nThis properly forwards SMC events to EL2 when PSCI is provided by QEMU\nitself and, thus, ARM_FEATURE_EL3 is off.\n\nFound and tested with the Jailhouse hypervisor.\n\nSigned-off-by: Jan Kiszka \n---\n target/arm/helper.c | 2 +-\n target/arm/op_helper.c | 8 ++++----\n target/arm/psci.c | 6 ++++++\n 3 files changed, 11 insertions(+), 5 deletions(-)","diff":"diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 4f41841ef6..8c3929762c 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -3717,7 +3717,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)\n \n if (arm_feature(env, ARM_FEATURE_EL3)) {\n valid_mask &= ~HCR_HCD;\n- } else {\n+ } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {\n valid_mask &= ~HCR_TSC;\n }\n \ndiff --git a/target/arm/op_helper.c b/target/arm/op_helper.c\nindex 6a60464ab9..4b0ef6a234 100644\n--- a/target/arm/op_helper.c\n+++ b/target/arm/op_helper.c\n@@ -960,12 +960,12 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)\n return;\n }\n \n- if (!arm_feature(env, ARM_FEATURE_EL3)) {\n- /* If we have no EL3 then SMC always UNDEFs */\n- undef = true;\n- } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {\n+ if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {\n /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */\n raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);\n+ } else if (!arm_feature(env, ARM_FEATURE_EL3)) {\n+ /* If we have no EL3 then SMC always UNDEFs */\n+ undef = true;\n }\n \n if (undef) {\ndiff --git a/target/arm/psci.c b/target/arm/psci.c\nindex fc34b263d3..637987ff46 100644\n--- a/target/arm/psci.c\n+++ b/target/arm/psci.c\n@@ -35,6 +35,8 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)\n */\n CPUARMState *env = &cpu->env;\n uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];\n+ int cur_el = arm_current_el(env);\n+ bool secure = arm_is_secure(env);\n \n switch (excp_type) {\n case EXCP_HVC:\n@@ -46,6 +48,10 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)\n if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {\n return false;\n }\n+ if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {\n+ /* The EL2 will handle this. */\n+ return false;\n+ }\n break;\n default:\n return false;\n","prefixes":[]}