{"id":814770,"url":"http://patchwork.ozlabs.org/api/1.2/patches/814770/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/20170918042157.19062-1-stewart@linux.vnet.ibm.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/1.2/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918042157.19062-1-stewart@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-18T04:21:57","name":"PHB4: Default to PCIe GEN3 on POWER9 DD2.00","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"b64caec61d4ac19239816b57f515ace82402ba37","submitter":{"id":48041,"url":"http://patchwork.ozlabs.org/api/1.2/people/48041/?format=json","name":"Stewart Smith","email":"stewart@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/20170918042157.19062-1-stewart@linux.vnet.ibm.com/mbox/","series":[{"id":3558,"url":"http://patchwork.ozlabs.org/api/1.2/series/3558/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/list/?series=3558","date":"2017-09-18T04:21:57","name":"PHB4: Default to PCIe GEN3 on POWER9 DD2.00","version":1,"mbox":"http://patchwork.ozlabs.org/series/3558/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814770/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814770/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwXsN02kxz9sBZ\n\tfor ;\n\tMon, 18 Sep 2017 14:22:16 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xwXsM4CtxzDrXg\n\tfor ;\n\tMon, 18 Sep 2017 14:22:15 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xwXsG15s8zDrWC\n\tfor ; Mon, 18 Sep 2017 14:22:09 +1000 (AEST)","from pps.filterd (m0098404.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8I4Kt7m015618\n\tfor ; Mon, 18 Sep 2017 00:22:07 -0400","from e37.co.us.ibm.com (e37.co.us.ibm.com [32.97.110.158])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2d1n38knyu-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Mon, 18 Sep 2017 00:22:06 -0400","from localhost\n\tby e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tSun, 17 Sep 2017 22:22:03 -0600","from b03ledav005.gho.boulder.ibm.com\n\t(b03ledav005.gho.boulder.ibm.com [9.17.130.236])\n\tby b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v8I4M23d459014; Sun, 17 Sep 2017 21:22:02 -0700","from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 88402BE039;\n\tSun, 17 Sep 2017 22:22:02 -0600 (MDT)","from birb.localdomain (unknown [9.185.16.148])\n\tby b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP id 116CCBE03B;\n\tSun, 17 Sep 2017 22:22:02 -0600 (MDT)","by birb.localdomain (Postfix, from userid 1000)\n\tid 5E3BB4F0F8F; Mon, 18 Sep 2017 14:21:58 +1000 (AEST)"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=stewart@linux.vnet.ibm.com; receiver=)","From":"Stewart Smith ","To":"skiboot@lists.ozlabs.org","Date":"Mon, 18 Sep 2017 14:21:57 +1000","X-Mailer":"git-send-email 2.13.5","X-TM-AS-GCONF":"00","x-cbid":"17091804-0024-0000-0000-0000173555AF","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007754; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000229; SDB=6.00918621; UDB=6.00461465;\n\tIPR=6.00698849; \n\tBA=6.00005593; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017190;\n\tXFM=3.00000015; UTC=2017-09-18 04:22:04","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17091804-0025-0000-0000-00004CC25326","Message-Id":"<20170918042157.19062-1-stewart@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-17_16:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709180062","Subject":"[Skiboot] [PATCH] PHB4: Default to PCIe GEN3 on POWER9 DD2.00","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"},"content":"You can use the NVRAM override for DD2.00 screened parts.\n\nSigned-off-by: Stewart Smith \n---\n hw/phb4.c | 6 ++++++\n 1 file changed, 6 insertions(+)","diff":"diff --git a/hw/phb4.c b/hw/phb4.c\nindex fea9125699fe..5371949fd997 100644\n--- a/hw/phb4.c\n+++ b/hw/phb4.c\n@@ -4741,12 +4741,14 @@ static void phb4_create(struct dt_node *np)\n \tchar *path;\n \tuint32_t irq_base, irq_flags;\n \tint i;\n+\tstruct proc_chip *chip;\n \n \tassert(p);\n \n \t/* Populate base stuff */\n \tp->index = dt_prop_get_u32(np, \"ibm,phb-index\");\n \tp->chip_id = dt_prop_get_u32(np, \"ibm,chip-id\");\n+\tchip = get_chip(p->chip_id);\n \tp->regs = (void *)dt_get_address(np, 0, NULL);\n \tp->int_mmio = (void *)dt_get_address(np, 1, NULL);\n \tp->phb.dt_node = np;\n@@ -4833,6 +4835,10 @@ static void phb4_create(struct dt_node *np)\n \tp->max_link_speed = 4;\n \tif (p->rev == PHB4_REV_NIMBUS_DD10)\n \t\tp->max_link_speed = 2;\n+\tif (p->rev == PHB4_REV_NIMBUS_DD20 && chip->ec_rev == 0) {\n+\t\tp->max_link_speed = 3;\n+\t\tPHBINF(p, \"Default max link speed for P9 DD2.00 is GEN3\\n\");\n+\t}\n \tif (dt_has_node_property(np, \"ibm,max-link-speed\", NULL))\n \t\tp->max_link_speed = dt_prop_get_u32(np, \"ibm,max-link-speed\");\n \tif (pcie_max_link_speed)\n","prefixes":[]}