{"id":814762,"url":"http://patchwork.ozlabs.org/api/1.2/patches/814762/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170918032815.25626-1-anarsoul@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918032815.25626-1-anarsoul@gmail.com>","list_archive_url":null,"date":"2017-09-18T03:28:13","name":"[U-Boot,1/3] pwm: sunxi: add support for PWM found on Allwinner A64 and H3","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"e18eb469b6e4feb1ada990bda235da67eb8c8591","submitter":{"id":6930,"url":"http://patchwork.ozlabs.org/api/1.2/people/6930/?format=json","name":"Vasily Khoruzhick","email":"anarsoul@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170918032815.25626-1-anarsoul@gmail.com/mbox/","series":[{"id":3556,"url":"http://patchwork.ozlabs.org/api/1.2/series/3556/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3556","date":"2017-09-18T03:28:13","name":"[U-Boot,1/3] pwm: sunxi: add support for PWM found on Allwinner A64 and H3","version":1,"mbox":"http://patchwork.ozlabs.org/series/3556/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814762/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814762/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"This commit adds basic support for PWM found on Allwinner A64 and H3\n\nSigned-off-by: Vasily Khoruzhick \n---\n arch/arm/include/asm/arch-sunxi/gpio.h | 1 +\n arch/arm/include/asm/arch-sunxi/pwm.h | 12 +++\n arch/arm/mach-sunxi/board.c | 11 +++\n drivers/pwm/Kconfig | 7 ++\n drivers/pwm/Makefile | 1 +\n drivers/pwm/sunxi_pwm.c | 174 +++++++++++++++++++++++++++++++++\n 6 files changed, 206 insertions(+)\n create mode 100644 drivers/pwm/sunxi_pwm.c","diff":"diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h\nindex 24f85206c8..7265d18099 100644\n--- a/arch/arm/include/asm/arch-sunxi/gpio.h\n+++ b/arch/arm/include/asm/arch-sunxi/gpio.h\n@@ -173,6 +173,7 @@ enum sunxi_gpio_number {\n #define SUN8I_GPD_SDC1\t\t3\n #define SUNXI_GPD_LCD0\t\t2\n #define SUNXI_GPD_LVDS0\t\t3\n+#define SUNXI_GPD_PWM\t\t2\n \n #define SUN5I_GPE_SDC2\t\t3\n #define SUN8I_GPE_TWI2\t\t3\ndiff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h\nindex 5884b5dbe7..673e0eb7b5 100644\n--- a/arch/arm/include/asm/arch-sunxi/pwm.h\n+++ b/arch/arm/include/asm/arch-sunxi/pwm.h\n@@ -11,8 +11,15 @@\n #define SUNXI_PWM_CH0_PERIOD\t\t(SUNXI_PWM_BASE + 4)\n \n #define SUNXI_PWM_CTRL_PRESCALE0(x)\t((x) & 0xf)\n+#define SUNXI_PWM_CTRL_PRESCALE0_MASK\t(0xf)\n #define SUNXI_PWM_CTRL_ENABLE0\t\t(0x5 << 4)\n #define SUNXI_PWM_CTRL_POLARITY0(x)\t((x) << 5)\n+#define SUNXI_PWM_CTRL_POLARITY0_MASK\t(1 << 5)\n+#define SUNXI_PWM_CTRL_CLK_GATE\t\t(1 << 6)\n+\n+#define SUNXI_PWM_CH0_PERIOD_MAX\t(0xffff)\n+#define SUNXI_PWM_CH0_PERIOD_PRD(x)\t((x & 0xffff) << 16)\n+#define SUNXI_PWM_CH0_PERIOD_DUTY(x)\t((x) & 0xffff)\n \n #define SUNXI_PWM_PERIOD_80PCT\t\t0x04af03c0\n \n@@ -31,4 +38,9 @@\n #define SUNXI_PWM_MUX\t\t\tSUN8I_GPH_PWM\n #endif\n \n+struct sunxi_pwm {\n+\tu32 ctrl;\n+\tu32 ch0_period;\n+};\n+\n #endif\ndiff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c\nindex 65b1ebd837..a85f973a46 100644\n--- a/arch/arm/mach-sunxi/board.c\n+++ b/arch/arm/mach-sunxi/board.c\n@@ -141,6 +141,16 @@ static int gpio_init(void)\n \treturn 0;\n }\n \n+static int pwm_init(void)\n+{\n+#ifdef CONFIG_PWM_SUNXI\n+#ifdef CONFIG_MACH_SUN50I\n+\tsunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);\n+#endif\n+#endif\n+\treturn 0;\n+}\n+\n #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)\n static int spl_board_load_image(struct spl_image_info *spl_image,\n \t\t\t\tstruct spl_boot_device *bootdev)\n@@ -204,6 +214,7 @@ void s_init(void)\n \tclock_init();\n \ttimer_init();\n \tgpio_init();\n+\tpwm_init();\n #ifndef CONFIG_DM_I2C\n \ti2c_init_board();\n #endif\ndiff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig\nindex e827558052..67e3f355e7 100644\n--- a/drivers/pwm/Kconfig\n+++ b/drivers/pwm/Kconfig\n@@ -43,3 +43,10 @@ config PWM_TEGRA\n \t four channels with a programmable period and duty cycle. Only a\n \t 32KHz clock is supported by the driver but the duty cycle is\n \t configurable.\n+\n+config PWM_SUNXI\n+\tbool \"Enable support for the Allwinner Sunxi PWM\"\n+\tdepends on DM_PWM\n+\thelp\n+\t This PWM is found on A64 and other Allwinner SoCs. It supports a\n+\t programmable period and duty cycle. A 32-bit counter is used.\ndiff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile\nindex 29d59916cb..1a8f8a58bc 100644\n--- a/drivers/pwm/Makefile\n+++ b/drivers/pwm/Makefile\n@@ -17,3 +17,4 @@ obj-$(CONFIG_PWM_IMX)\t\t+= pwm-imx.o pwm-imx-util.o\n obj-$(CONFIG_PWM_ROCKCHIP)\t+= rk_pwm.o\n obj-$(CONFIG_PWM_SANDBOX)\t+= sandbox_pwm.o\n obj-$(CONFIG_PWM_TEGRA)\t\t+= tegra_pwm.o\n+obj-$(CONFIG_PWM_SUNXI)\t\t+= sunxi_pwm.o\ndiff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c\nnew file mode 100644\nindex 0000000000..3e6d69fa1c\n--- /dev/null\n+++ b/drivers/pwm/sunxi_pwm.c\n@@ -0,0 +1,174 @@\n+/*\n+ * Copyright (c) 2017 Vasily Khoruzhick \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+struct sunxi_pwm_priv {\n+\tstruct sunxi_pwm *regs;\n+\tulong freq;\n+\tbool invert;\n+\tuint32_t prescaler;\n+};\n+\n+static const uint32_t prescaler_table[] = {\n+\t120,\t/* 0000 */\n+\t180,\t/* 0001 */\n+\t240,\t/* 0010 */\n+\t360,\t/* 0011 */\n+\t480,\t/* 0100 */\n+\t0,\t/* 0101 */\n+\t0,\t/* 0110 */\n+\t0,\t/* 0111 */\n+\t12000,\t/* 1000 */\n+\t24000,\t/* 1001 */\n+\t36000,\t/* 1010 */\n+\t48000,\t/* 1011 */\n+\t72000,\t/* 1100 */\n+\t0,\t/* 1101 */\n+\t0,\t/* 1110 */\n+\t1,\t/* 1111 */\n+};\n+\n+static const uint64_t nsecs_per_sec = 1000000000L;\n+\n+static int sunxi_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\n+\tdebug(\"%s: polarity=%u\\n\", __func__, polarity);\n+\tpriv->invert = polarity;\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,\n+\t\t\t uint duty_ns)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\tstruct sunxi_pwm *regs = priv->regs;\n+\tint prescaler;\n+\tu32 v, period, duty;\n+\tuint64_t div = 0, pval = 0, scaled_freq = 0;\n+\n+\tdebug(\"%s: period_ns=%u, duty_ns=%u\\n\", __func__, period_ns, duty_ns);\n+\n+\tfor (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK; prescaler++) {\n+\t\tif (!prescaler_table[prescaler])\n+\t\t\tcontinue;\n+\t\tdiv = priv->freq;\n+\t\tpval = prescaler_table[prescaler];\n+\t\tscaled_freq = lldiv(div, pval);\n+\t\tdiv = scaled_freq * period_ns;\n+\t\tdiv = lldiv(div, nsecs_per_sec);\n+\t\tif (div - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (div - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {\n+\t\tdebug(\"%s: failed to find prescaler value\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tperiod = div;\n+\tdiv = scaled_freq * duty_ns;\n+\tdiv = lldiv(div, nsecs_per_sec);\n+\tduty = div;\n+\n+\tif (priv->prescaler != prescaler) {\n+\t\t/* Mask clock to update prescaler */\n+\t\tv = readl(®s->ctrl);\n+\t\tv &= ~SUNXI_PWM_CTRL_CLK_GATE;\n+\t\twritel(v, ®s->ctrl);\n+\t\tv &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;\n+\t\tv |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);\n+\t\twritel(v, ®s->ctrl);\n+\t\tv |= SUNXI_PWM_CTRL_CLK_GATE;\n+\t\twritel(v, ®s->ctrl);\n+\t\tpriv->prescaler = prescaler;\n+\t}\n+\n+\twritel(SUNXI_PWM_CH0_PERIOD_PRD(period) |\n+\t SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period);\n+\n+\tdebug(\"%s: prescaler: %d, period: %d, duty: %d\\n\", __func__, priv->prescaler,\n+\t period, duty);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\tstruct sunxi_pwm *regs = priv->regs;\n+\tuint32_t v;\n+\n+\tdebug(\"%s: Enable '%s'\\n\", __func__, dev->name);\n+\n+\tv = readl(®s->ctrl);\n+\tif (!enable) {\n+\t\tv &= ~SUNXI_PWM_CTRL_ENABLE0;\n+\t\twritel(v, ®s->ctrl);\n+\t\treturn 0;\n+\t}\n+\n+\tv &= ~SUNXI_PWM_CTRL_POLARITY0_MASK;\n+\tv |= priv->invert ? SUNXI_PWM_CTRL_POLARITY0(0) :\n+\t\t SUNXI_PWM_CTRL_POLARITY0(1);\n+\tv |= SUNXI_PWM_CTRL_ENABLE0;\n+\twritel(v, ®s->ctrl);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_probe(struct udevice *dev)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->freq = 24000000;\n+\n+\treturn 0;\n+}\n+\n+static const struct pwm_ops sunxi_pwm_ops = {\n+\t.set_invert\t= sunxi_pwm_set_invert,\n+\t.set_config\t= sunxi_pwm_set_config,\n+\t.set_enable\t= sunxi_pwm_set_enable,\n+};\n+\n+static const struct udevice_id sunxi_pwm_ids[] = {\n+\t{ .compatible = \"allwinner,sun8i-h3-pwm\" },\n+\t{ .compatible = \"allwinner,sun50i-a64-pwm\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(sunxi_pwm) = {\n+\t.name\t= \"sunxi_pwm\",\n+\t.id\t= UCLASS_PWM,\n+\t.of_match = sunxi_pwm_ids,\n+\t.ops\t= &sunxi_pwm_ops,\n+\t.ofdata_to_platdata\t= sunxi_pwm_ofdata_to_platdata,\n+\t.probe\t\t= sunxi_pwm_probe,\n+\t.priv_auto_alloc_size\t= sizeof(struct sunxi_pwm_priv),\n+};\n","prefixes":["U-Boot","1/3"]}