{"id":814761,"url":"http://patchwork.ozlabs.org/api/1.2/patches/814761/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170918032145.25349-5-anarsoul@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918032145.25349-5-anarsoul@gmail.com>","list_archive_url":null,"date":"2017-09-18T03:21:45","name":"[U-Boot,5/5] sunxi: video: add LCD support to DE2 driver","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"ea533162141cf16647b76b8c2db82c1fcf6135be","submitter":{"id":6930,"url":"http://patchwork.ozlabs.org/api/1.2/people/6930/?format=json","name":"Vasily Khoruzhick","email":"anarsoul@gmail.com"},"delegate":{"id":1700,"url":"http://patchwork.ozlabs.org/api/1.2/users/1700/?format=json","username":"ag","first_name":"Anatolij","last_name":"Gustschin","email":"agust@denx.de"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170918032145.25349-5-anarsoul@gmail.com/mbox/","series":[{"id":3555,"url":"http://patchwork.ozlabs.org/api/1.2/series/3555/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3555","date":"2017-09-18T03:21:41","name":"[U-Boot,1/5] dm: video: bridge: add operation to read EDID","version":1,"mbox":"http://patchwork.ozlabs.org/series/3555/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814761/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814761/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Extend DE2 driver with LCD support\n\nSigned-off-by: Vasily Khoruzhick \n---\n arch/arm/mach-sunxi/Kconfig | 2 +-\n drivers/video/sunxi/Makefile | 2 +-\n drivers/video/sunxi/sunxi_de2.c | 17 +++++\n drivers/video/sunxi/sunxi_lcd.c | 142 ++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 161 insertions(+), 2 deletions(-)\n create mode 100644 drivers/video/sunxi/sunxi_lcd.c","diff":"diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig\nindex 2309f59999..06d697e3a7 100644\n--- a/arch/arm/mach-sunxi/Kconfig\n+++ b/arch/arm/mach-sunxi/Kconfig\n@@ -680,7 +680,7 @@ config VIDEO_LCD_MODE\n \n config VIDEO_LCD_DCLK_PHASE\n \tint \"LCD panel display clock phase\"\n-\tdepends on VIDEO\n+\tdepends on VIDEO || DM_VIDEO\n \tdefault 1\n \t---help---\n \tSelect LCD panel display clock phase shift, range 0-3.\ndiff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile\nindex 0d64c2021f..8c91766c24 100644\n--- a/drivers/video/sunxi/Makefile\n+++ b/drivers/video/sunxi/Makefile\n@@ -6,4 +6,4 @@\n #\n \n obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o\n-obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o\n+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o sunxi_lcd.o\ndiff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c\nindex ee67764ac5..a838bbacd1 100644\n--- a/drivers/video/sunxi/sunxi_de2.c\n+++ b/drivers/video/sunxi/sunxi_de2.c\n@@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)\n \tif (!(gd->flags & GD_FLG_RELOC))\n \t\treturn 0;\n \n+\tret = uclass_find_device_by_name(UCLASS_DISPLAY,\n+\t\t\t\t\t \"sunxi_lcd\", &disp);\n+\tif (!ret) {\n+\t\tint mux;\n+\n+\t\tmux = 0;\n+\n+\t\tret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,\n+\t\t false);\n+\t\tif (!ret) {\n+\t\t\tvideo_set_flush_dcache(dev, 1);\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\tdebug(\"%s: lcd display not found (ret=%d)\\n\", __func__, ret);\n+\n \tret = uclass_find_device_by_name(UCLASS_DISPLAY,\n \t\t\t\t\t \"sunxi_dw_hdmi\", &disp);\n \tif (!ret) {\ndiff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c\nnew file mode 100644\nindex 0000000000..154eb5835e\n--- /dev/null\n+++ b/drivers/video/sunxi/sunxi_lcd.c\n@@ -0,0 +1,142 @@\n+/*\n+ * Allwinner LCD driver\n+ *\n+ * (C) Copyright 2017 Vasily Khoruzhick \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+struct sunxi_lcd_priv {\n+\tstruct display_timing timing;\n+\tint panel_bpp;\n+};\n+\n+static void sunxi_lcdc_config_pinmux(void)\n+{\n+\tint pin;\n+\tfor (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {\n+\t\tsunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);\n+\t\tsunxi_gpio_set_drv(pin, 3);\n+\t}\n+}\n+\n+static int sunxi_lcd_enable(struct udevice *dev, int bpp,\n+ const struct display_timing *edid)\n+{\n+\tstruct sunxi_ccm_reg * const ccm =\n+\t (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n+\tstruct sunxi_lcdc_reg * const lcdc =\n+\t (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;\n+\tstruct sunxi_lcd_priv *priv = dev_get_priv(dev);\n+\tstruct udevice *backlight;\n+\tint clk_div, clk_double, ret;\n+\n+\t/* Reset off */\n+\tsetbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);\n+\n+\t/* Clock on */\n+\tsetbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);\n+\n+\tlcdc_init(lcdc);\n+\tsunxi_lcdc_config_pinmux();\n+\tlcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000,\n+\t &clk_div, &clk_double);\n+\tlcdc_tcon0_mode_set(lcdc, edid, clk_div, false,\n+\t priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE);\n+\tlcdc_enable(lcdc, priv->panel_bpp);\n+\n+\tret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight);\n+\tif (!ret)\n+\t\tbacklight_enable(backlight);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_lcd_read_timing(struct udevice *dev,\n+ struct display_timing *timing)\n+{\n+\tstruct sunxi_lcd_priv *priv = dev_get_priv(dev);\n+\tmemcpy(timing, &priv->timing, sizeof(struct display_timing));\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_lcd_probe(struct udevice *dev)\n+{\n+\tstruct udevice *cdev;\n+\tstruct sunxi_lcd_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\t/* make sure that clock is active */\n+\tclock_set_pll10(432000000);\n+\n+#ifdef CONFIG_VIDEO_BRIDGE\n+\t/* Try to get timings from bridge first */\n+\tret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &cdev);\n+\tif (!ret) {\n+\t\tu8 edid[EDID_SIZE];\n+\t\tint channel_bpp;\n+\n+\t\tret = video_bridge_attach(cdev);\n+\t\tif (ret) {\n+\t\t\tdebug(\"video bridge attach failed: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tret = video_bridge_read_edid(cdev, edid, EDID_SIZE);\n+\t\tif (ret <= 0) {\n+\t\t\tdebug(\"video bridge failed to read edid: %d\\n\", ret);\n+\t\t\treturn ret ? ret : -EIO;\n+\t\t}\n+\t\tret = edid_get_timing(edid, ret, &priv->timing, &channel_bpp);\n+\t\tpriv->panel_bpp = channel_bpp * 3;\n+\t\treturn ret;\n+\t}\n+\tdebug(\"video bridge not found: %d\\n\", ret);\n+#endif\n+\t/* Fallback to timings from DT if there's no bridge */\n+\tret = uclass_get_device(UCLASS_PANEL, 0, &cdev);\n+\tif (ret) {\n+\t\tdebug(\"video panel not found: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev),\n+\t\t\t\t\t 0, &priv->timing)) {\n+\t\tdebug(\"%s: Failed to decode display timing\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\tpriv->panel_bpp = 16;\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_display_ops sunxi_lcd_ops = {\n+ .read_timing = sunxi_lcd_read_timing,\n+ .enable = sunxi_lcd_enable,\n+};\n+\n+U_BOOT_DRIVER(sunxi_lcd) = {\n+\t.name = \"sunxi_lcd\",\n+\t.id = UCLASS_DISPLAY,\n+\t.ops = &sunxi_lcd_ops,\n+\t.probe = sunxi_lcd_probe,\n+\t.priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),\n+};\n+\n+#ifdef CONFIG_MACH_SUN50I\n+U_BOOT_DEVICE(sunxi_lcd) = {\n+\t.name = \"sunxi_lcd\"\n+};\n+#endif\n","prefixes":["U-Boot","5/5"]}