{"id":814758,"url":"http://patchwork.ozlabs.org/api/1.2/patches/814758/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170918032145.25349-2-anarsoul@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170918032145.25349-2-anarsoul@gmail.com>","list_archive_url":null,"date":"2017-09-18T03:21:42","name":"[U-Boot,2/5] video: anx9804: split out registers definitions into a separate header","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"67fce4c1c68ce06da92bd1c05ca184f37a12e5ec","submitter":{"id":6930,"url":"http://patchwork.ozlabs.org/api/1.2/people/6930/?format=json","name":"Vasily Khoruzhick","email":"anarsoul@gmail.com"},"delegate":{"id":1700,"url":"http://patchwork.ozlabs.org/api/1.2/users/1700/?format=json","username":"ag","first_name":"Anatolij","last_name":"Gustschin","email":"agust@denx.de"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170918032145.25349-2-anarsoul@gmail.com/mbox/","series":[{"id":3555,"url":"http://patchwork.ozlabs.org/api/1.2/series/3555/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=3555","date":"2017-09-18T03:21:41","name":"[U-Boot,1/5] dm: video: bridge: add operation to read EDID","version":1,"mbox":"http://patchwork.ozlabs.org/series/3555/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/814758/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/814758/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KMMPP6yW\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwWXd6h1Cz9ryr\n\tfor ;\n\tMon, 18 Sep 2017 13:22:41 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 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-0700","Message-Id":"<20170918032145.25349-2-anarsoul@gmail.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170918032145.25349-1-anarsoul@gmail.com>","References":"<20170918032145.25349-1-anarsoul@gmail.com>","Subject":"[U-Boot] [PATCH 2/5] video: anx9804: split out registers\n\tdefinitions into a separate header","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"This header will be used in anx6345 driver\n\nSigned-off-by: Vasily Khoruzhick \n---\n drivers/video/anx9804.c | 54 +--------------------------\n include/anx98xx-edp.h | 98 +++++++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 99 insertions(+), 53 deletions(-)\n create mode 100644 include/anx98xx-edp.h","diff":"diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c\nindex 37ad69a039..67f7da7d18 100755\n--- a/drivers/video/anx9804.c\n+++ b/drivers/video/anx9804.c\n@@ -12,61 +12,9 @@\n \n #include \n #include \n+#include \n #include \"anx9804.h\"\n \n-/* Registers at i2c address 0x38 */\n-\n-#define ANX9804_HDCP_CONTROL_0_REG\t\t\t\t0x01\n-\n-#define ANX9804_SYS_CTRL2_REG\t\t\t\t\t0x81\n-#define ANX9804_SYS_CTRL2_CHA_STA\t\t\t\t0x04\n-\n-#define ANX9804_SYS_CTRL3_REG\t\t\t\t\t0x82\n-#define ANX9804_SYS_CTRL3_VALID_CTRL\t\t\t\tBIT(0)\n-#define ANX9804_SYS_CTRL3_F_VALID\t\t\t\tBIT(1)\n-#define ANX9804_SYS_CTRL3_HPD_CTRL\t\t\t\tBIT(4)\n-#define ANX9804_SYS_CTRL3_F_HPD\t\t\t\t\tBIT(5)\n-\n-#define ANX9804_LINK_BW_SET_REG\t\t\t\t\t0xa0\n-#define ANX9804_LANE_COUNT_SET_REG\t\t\t\t0xa1\n-#define ANX9804_TRAINING_PTN_SET_REG\t\t\t\t0xa2\n-#define ANX9804_TRAINING_LANE0_SET_REG\t\t\t\t0xa3\n-#define ANX9804_TRAINING_LANE1_SET_REG\t\t\t\t0xa4\n-#define ANX9804_TRAINING_LANE2_SET_REG\t\t\t\t0xa5\n-#define ANX9804_TRAINING_LANE3_SET_REG\t\t\t\t0xa6\n-\n-#define ANX9804_LINK_TRAINING_CTRL_REG\t\t\t\t0xa8\n-#define ANX9804_LINK_TRAINING_CTRL_EN\t\t\t\tBIT(0)\n-\n-#define ANX9804_LINK_DEBUG_REG\t\t\t\t\t0xb8\n-#define ANX9804_PLL_CTRL_REG\t\t\t\t\t0xc7\t\n-#define ANX9804_ANALOG_POWER_DOWN_REG\t\t\t\t0xc8\n-\n-/* Registers at i2c address 0x39 */\n-\n-#define ANX9804_DEV_IDH_REG\t\t\t\t\t0x03\n-\n-#define ANX9804_POWERD_CTRL_REG\t\t\t\t\t0x05\n-#define ANX9804_POWERD_AUDIO\t\t\t\t\tBIT(4)\n-\n-#define ANX9804_RST_CTRL_REG\t\t\t\t\t0x06\n-\n-#define ANX9804_RST_CTRL2_REG\t\t\t\t\t0x07\n-#define ANX9804_RST_CTRL2_AUX\t\t\t\t\tBIT(2)\n-#define ANX9804_RST_CTRL2_AC_MODE\t\t\t\tBIT(6)\n-\n-#define ANX9804_VID_CTRL1_REG\t\t\t\t\t0x08\n-#define ANX9804_VID_CTRL1_VID_EN\t\t\t\tBIT(7)\n-#define ANX9804_VID_CTRL1_EDGE\t\t\t\t\tBIT(0)\n-\n-#define ANX9804_VID_CTRL2_REG\t\t\t\t\t0x09\n-#define ANX9804_ANALOG_DEBUG_REG1\t\t\t\t0xdc\n-#define ANX9804_ANALOG_DEBUG_REG3\t\t\t\t0xde\n-#define ANX9804_PLL_FILTER_CTRL1\t\t\t\t0xdf\n-#define ANX9804_PLL_FILTER_CTRL3\t\t\t\t0xe1\n-#define ANX9804_PLL_FILTER_CTRL\t\t\t\t\t0xe2\n-#define ANX9804_PLL_CTRL3\t\t\t\t\t0xe6\n-\n /**\n * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip\n *\ndiff --git a/include/anx98xx-edp.h b/include/anx98xx-edp.h\nnew file mode 100644\nindex 0000000000..f7e8baa167\n--- /dev/null\n+++ b/include/anx98xx-edp.h\n@@ -0,0 +1,98 @@\n+/*\n+ * Copyright (C) 2015 Hans de Goede \n+ * Copyright (C) 2017 Vasily Khoruzhick \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/* Registers at i2c address 0x38 */\n+\n+#define ANX9804_HDCP_CONTROL_0_REG\t\t\t\t0x01\n+\n+#define ANX9804_SYS_CTRL1_REG\t\t\t\t\t0x80\n+#define ANX9804_SYS_CTRL1_PD_IO\t\t\t\t\t0x80\n+#define ANX9804_SYS_CTRL1_PD_VID\t\t\t\t0x40\n+#define ANX9804_SYS_CTRL1_PD_LINK\t\t\t\t0x20\n+#define ANX9804_SYS_CTRL1_PD_TOTAL\t\t\t\t0x10\n+#define ANX9804_SYS_CTRL1_MODE_SEL\t\t\t\t0x08\n+#define ANX9804_SYS_CTRL1_DET_STA\t\t\t\t0x04\n+#define ANX9804_SYS_CTRL1_FORCE_DET\t\t\t\t0x02\n+#define ANX9804_SYS_CTRL1_DET_CTRL\t\t\t\t0x01\n+\n+#define ANX9804_SYS_CTRL2_REG\t\t\t\t\t0x81\n+#define ANX9804_SYS_CTRL2_CHA_STA\t\t\t\t0x04\n+\n+#define ANX9804_SYS_CTRL3_REG\t\t\t\t\t0x82\n+#define ANX9804_SYS_CTRL3_VALID_CTRL\t\t\t\tBIT(0)\n+#define ANX9804_SYS_CTRL3_F_VALID\t\t\t\tBIT(1)\n+#define ANX9804_SYS_CTRL3_HPD_CTRL\t\t\t\tBIT(4)\n+#define ANX9804_SYS_CTRL3_F_HPD\t\t\t\t\tBIT(5)\n+\n+#define ANX9804_LINK_BW_SET_REG\t\t\t\t\t0xa0\n+#define ANX9804_LANE_COUNT_SET_REG\t\t\t\t0xa1\n+#define ANX9804_TRAINING_PTN_SET_REG\t\t\t\t0xa2\n+#define ANX9804_TRAINING_LANE0_SET_REG\t\t\t\t0xa3\n+#define ANX9804_TRAINING_LANE1_SET_REG\t\t\t\t0xa4\n+#define ANX9804_TRAINING_LANE2_SET_REG\t\t\t\t0xa5\n+#define ANX9804_TRAINING_LANE3_SET_REG\t\t\t\t0xa6\n+\n+#define ANX9804_LINK_TRAINING_CTRL_REG\t\t\t\t0xa8\n+#define ANX9804_LINK_TRAINING_CTRL_EN\t\t\t\tBIT(0)\n+\n+#define ANX9804_LINK_DEBUG_REG\t\t\t\t\t0xb8\n+#define ANX9804_PLL_CTRL_REG\t\t\t\t\t0xc7\n+#define ANX9804_ANALOG_POWER_DOWN_REG\t\t\t\t0xc8\n+\n+#define ANX9804_AUX_CH_STA\t\t\t\t\t0xe0\n+#define ANX9804_AUX_BUSY\t\t\t\t\tBIT(4)\n+#define ANX9804_AUX_STATUS_MASK\t\t\t\t\t0x0f\n+\n+#define ANX9804_DP_AUX_RX_COMM\t\t\t\t\t0xe3\n+#define ANX9804_AUX_RX_COMM_I2C_DEFER\t\t\t\tBIT(3)\n+#define ANX9804_AUX_RX_COMM_AUX_DEFER\t\t\t\tBIT(1)\n+\n+#define ANX9804_DP_AUX_CH_CTL_1\t\t\t\t\t0xe5\n+#define ANX9804_AUX_LENGTH(x)\t\t\t\t\t(((x - 1) & 0x0f) << 4)\n+#define ANX9804_AUX_TX_COMM_MASK\t\t\t\t0x0f\n+#define ANX9804_AUX_TX_COMM_DP_TRANSACTION\t\t\tBIT(3)\n+#define ANX9804_AUX_TX_COMM_MOT\t\t\t\t\tBIT(2)\n+#define ANX9804_AUX_TX_COMM_READ\t\t\t\tBIT(0)\n+\n+#define ANX9804_DP_AUX_ADDR_7_0\t\t\t\t\t0xe6\n+#define ANX9804_DP_AUX_ADDR_15_8\t\t\t\t0xe7\n+#define ANX9804_DP_AUX_ADDR_19_16\t\t\t\t0xe8\n+\n+#define ANX9804_DP_AUX_CH_CTL_2\t\t\t\t\t0xe9\n+#define ANX9804_ADDR_ONLY\t\t\t\t\tBIT(1)\n+#define ANX9804_AUX_EN\t\t\t\t\t\tBIT(0)\n+\n+#define ANX9804_BUF_DATA_0\t\t\t\t\t0xf0\n+\n+/* Registers at i2c address 0x39 */\n+\n+#define ANX9804_DEV_IDH_REG\t\t\t\t\t0x03\n+\n+#define ANX9804_POWERD_CTRL_REG\t\t\t\t\t0x05\n+#define ANX9804_POWERD_AUDIO\t\t\t\t\tBIT(4)\n+\n+#define ANX9804_RST_CTRL_REG\t\t\t\t\t0x06\n+\n+#define ANX9804_RST_CTRL2_REG\t\t\t\t\t0x07\n+#define ANX9804_RST_CTRL2_AUX\t\t\t\t\tBIT(2)\n+#define ANX9804_RST_CTRL2_AC_MODE\t\t\t\tBIT(6)\n+\n+#define ANX9804_VID_CTRL1_REG\t\t\t\t\t0x08\n+#define ANX9804_VID_CTRL1_VID_EN\t\t\t\tBIT(7)\n+#define ANX9804_VID_CTRL1_EDGE\t\t\t\t\tBIT(0)\n+\n+#define ANX9804_VID_CTRL2_REG\t\t\t\t\t0x09\n+#define ANX9804_ANALOG_DEBUG_REG1\t\t\t\t0xdc\n+#define ANX9804_ANALOG_DEBUG_REG3\t\t\t\t0xde\n+#define ANX9804_PLL_FILTER_CTRL1\t\t\t\t0xdf\n+#define ANX9804_PLL_FILTER_CTRL3\t\t\t\t0xe1\n+#define ANX9804_PLL_FILTER_CTRL\t\t\t\t\t0xe2\n+#define ANX9804_PLL_CTRL3\t\t\t\t\t0xe6\n+\n+#define ANX9804_DP_INT_STA\t\t\t\t\t0xf7\n+#define ANX9804_RPLY_RECEIV\t\t\t\t\tBIT(1)\n+#define ANX9804_AUX_ERR\t\t\t\t\t\tBIT(0)\n","prefixes":["U-Boot","2/5"]}