{"id":813329,"url":"http://patchwork.ozlabs.org/api/1.2/patches/813329/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150529908530.10902.11619586029850482917.stgit@frigg.lan/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<150529908530.10902.11619586029850482917.stgit@frigg.lan>","list_archive_url":null,"date":"2017-09-13T10:38:05","name":"[v6,11/22] instrument: Track vCPUs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1b712190b5078434900347512a1232464492d96e","submitter":{"id":9099,"url":"http://patchwork.ozlabs.org/api/1.2/people/9099/?format=json","name":"Lluís Vilanova","email":"vilanova@ac.upc.edu"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150529908530.10902.11619586029850482917.stgit@frigg.lan/mbox/","series":[{"id":2857,"url":"http://patchwork.ozlabs.org/api/1.2/series/2857/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2857","date":"2017-09-13T09:53:43","name":"instrument: Add basic event instrumentation","version":6,"mbox":"http://patchwork.ozlabs.org/series/2857/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/813329/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/813329/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsdTn3rGrz9sNV\n\tfor ;\n\tWed, 13 Sep 2017 20:40:13 +1000 (AEST)","from localhost ([::1]:41449 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1ds55X-0007Bx-Iz\n\tfor incoming@patchwork.ozlabs.org; Wed, 13 Sep 2017 06:40:11 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:56540)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1ds53l-0006Dw-B0\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 06:38:23 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1ds53g-0001Zz-Ai\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 06:38:21 -0400","from roura.ac.upc.edu ([147.83.33.10]:35492 helo=roura.ac.upc.es)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1ds53g-0001YZ-0X\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 06:38:16 -0400","from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92])\n\tby roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v8DAcCLp008972;\n\tWed, 13 Sep 2017 12:38:12 +0200","from localhost (unknown [132.68.137.204])\n\tby correu-2.ac.upc.es (Postfix) with ESMTPSA id 8284439C;\n\tWed, 13 Sep 2017 12:38:06 +0200 (CEST)"],"From":"=?utf-8?b?TGx1w61z?= Vilanova ","To":"qemu-devel@nongnu.org","Date":"Wed, 13 Sep 2017 13:38:05 +0300","Message-Id":"<150529908530.10902.11619586029850482917.stgit@frigg.lan>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<150529642278.10902.18234057937634437857.stgit@frigg.lan>","References":"<150529642278.10902.18234057937634437857.stgit@frigg.lan>","User-Agent":"StGit/0.18","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","X-MIME-Autoconverted":"from 8bit to quoted-printable by roura.ac.upc.es id\n\tv8DAcCLp008972","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy]","X-Received-From":"147.83.33.10","Subject":"[Qemu-devel] [PATCH v6 11/22] instrument: Track vCPUs","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"Emilio G. Cota\" , Markus Armbruster ,\n\tStefan Hajnoczi , =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Keep a translation between instrumentation's QICPU and CPUState objects to avoid\nexposing QEMU's internals to instrumentation clients.\n\nSigned-off-by: Lluís Vilanova \n---\n cpus-common.c | 9 +++++++++\n instrument/control.c | 23 +++++++++++++++++++++++\n instrument/control.h | 36 ++++++++++++++++++++++++++++++++++++\n instrument/control.inc.h | 23 +++++++++++++++++++++++\n 4 files changed, 91 insertions(+)","diff":"diff --git a/cpus-common.c b/cpus-common.c\nindex 59f751ecf9..ec5f46cc3d 100644\n--- a/cpus-common.c\n+++ b/cpus-common.c\n@@ -22,6 +22,9 @@\n #include \"exec/cpu-common.h\"\n #include \"qom/cpu.h\"\n #include \"sysemu/cpus.h\"\n+#if defined(CONFIG_INSTRUMENT)\n+#include \"instrument/control.h\"\n+#endif\n \n static QemuMutex qemu_cpu_list_lock;\n static QemuCond exclusive_cond;\n@@ -84,6 +87,9 @@ void cpu_list_add(CPUState *cpu)\n } else {\n assert(!cpu_index_auto_assigned);\n }\n+#if defined(CONFIG_INSTRUMENT)\n+ instr_cpu_add(cpu);\n+#endif\n QTAILQ_INSERT_TAIL(&cpus, cpu, node);\n qemu_mutex_unlock(&qemu_cpu_list_lock);\n \n@@ -102,6 +108,9 @@ void cpu_list_remove(CPUState *cpu)\n assert(!(cpu_index_auto_assigned && cpu != QTAILQ_LAST(&cpus, CPUTailQ)));\n \n QTAILQ_REMOVE(&cpus, cpu, node);\n+#if defined(CONFIG_INSTRUMENT)\n+ instr_cpu_remove(cpu);\n+#endif\n cpu->cpu_index = UNASSIGNED_CPU_INDEX;\n qemu_mutex_unlock(&qemu_cpu_list_lock);\n }\ndiff --git a/instrument/control.c b/instrument/control.c\nindex 3630d6b3be..8cf2b4f967 100644\n--- a/instrument/control.c\n+++ b/instrument/control.c\n@@ -13,10 +13,33 @@\n #include \"instrument/load.h\"\n #include \"instrument/qemu-instr/control.h\"\n #include \"qemu/compiler.h\"\n+#include \"qom/cpu.h\"\n+\n \n __thread InstrState instr_cur_state;\n \n \n+unsigned int instr_cpus_count;\n+CPUState **instr_cpus;\n+\n+void instr_cpu_add(CPUState *vcpu)\n+{\n+ unsigned int idx = vcpu->cpu_index;\n+ if (idx >= instr_cpus_count) {\n+ instr_cpus_count = idx + 1;\n+ instr_cpus = realloc(instr_cpus,\n+ sizeof(*instr_cpus) * instr_cpus_count);\n+ }\n+ instr_cpus[idx] = vcpu;\n+}\n+\n+void instr_cpu_remove(CPUState *vcpu)\n+{\n+ unsigned int idx = vcpu->cpu_index;\n+ instr_cpus[idx] = NULL;\n+}\n+\n+\n qi_fini_fn instr_event__fini_fn;\n void *instr_event__fini_data;\n \ndiff --git a/instrument/control.h b/instrument/control.h\nindex f2b085f69b..57cea07fa7 100644\n--- a/instrument/control.h\n+++ b/instrument/control.h\n@@ -10,6 +10,42 @@\n #ifndef INSTRUMENT__CONTROL_H\n #define INSTRUMENT__CONTROL_H\n \n+#include \"qemu/typedefs.h\"\n+#include \"instrument/qemu-instr/types.h\"\n+\n+\n+/**\n+ * instr_cpu_add:\n+ *\n+ * Make @vcpu available to instrumentation clients.\n+ *\n+ * Precondition: cpu_list_lock().\n+ */\n+void instr_cpu_add(CPUState *vcpu);\n+\n+/**\n+ * instr_cpu_remove:\n+ *\n+ * Make @vcpu unavailable to instrumentation clients.\n+ *\n+ * Precondition: cpu_list_lock().\n+ */\n+void instr_cpu_remove(CPUState *vcpu);\n+\n+/**\n+ * instr_cpu_to_qicpu:\n+ *\n+ * Get the #QICPU corresponding to the given #CPUState.\n+ */\n+static inline QICPU instr_cpu_to_qicpu(CPUState *vcpu);\n+\n+/**\n+ * instr_cpu_from_qicpu:\n+ *\n+ * Get the #CPUState corresponding to the given #QICPU.\n+ */\n+static inline CPUState *instr_cpu_from_qicpu(QICPU vcpu);\n+\n \n /**\n * InstrState:\ndiff --git a/instrument/control.inc.h b/instrument/control.inc.h\nindex 0f649f4caa..45daae7d1d 100644\n--- a/instrument/control.inc.h\n+++ b/instrument/control.inc.h\n@@ -7,9 +7,32 @@\n * See the COPYING file in the top-level directory.\n */\n \n+#include \"qemu/osdep.h\"\n #include \"qemu/atomic.h\"\n #include \"qemu/compiler.h\"\n+#include \"qom/cpu.h\"\n #include \n+#include \n+\n+\n+extern unsigned int instr_cpus_count;\n+extern CPUState **instr_cpus;\n+\n+static inline QICPU instr_cpu_to_qicpu(CPUState *vcpu)\n+{\n+ uintptr_t idx = vcpu->cpu_index;\n+ return (QICPU)idx;\n+}\n+\n+static inline CPUState *instr_cpu_from_qicpu(QICPU vcpu)\n+{\n+ unsigned int idx = (uintptr_t)vcpu;\n+ if (idx >= instr_cpus_count) {\n+ return NULL;\n+ } else {\n+ return instr_cpus[idx];\n+ }\n+}\n \n \n extern __thread InstrState instr_cur_state;\n","prefixes":["v6","11/22"]}