{"id":812225,"url":"http://patchwork.ozlabs.org/api/1.2/patches/812225/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20170911061156.31872-1-drake@endlessm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.2/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170911061156.31872-1-drake@endlessm.com>","list_archive_url":null,"date":"2017-09-11T06:11:56","name":"pinctrl/amd: save pin registers over suspend/resume","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ed8002174bc8ad29a4ccc2f25fa2fd2793d25eca","submitter":{"id":64396,"url":"http://patchwork.ozlabs.org/api/1.2/people/64396/?format=json","name":"Daniel Drake","email":"drake@endlessm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20170911061156.31872-1-drake@endlessm.com/mbox/","series":[{"id":2438,"url":"http://patchwork.ozlabs.org/api/1.2/series/2438/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=2438","date":"2017-09-11T06:11:56","name":"pinctrl/amd: save pin registers over suspend/resume","version":1,"mbox":"http://patchwork.ozlabs.org/series/2438/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/812225/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/812225/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=endlessm-com.20150623.gappssmtp.com\n\theader.i=@endlessm-com.20150623.gappssmtp.com\n\theader.b=\"n3a+GUHf\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrHdS1Y6Gz9s76\n\tfor ;\n\tMon, 11 Sep 2017 16:12:12 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750806AbdIKGMJ (ORCPT );\n\tMon, 11 Sep 2017 02:12:09 -0400","from mail-pf0-f170.google.com ([209.85.192.170]:36699 \"EHLO\n\tmail-pf0-f170.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750748AbdIKGMI (ORCPT\n\t); Mon, 11 Sep 2017 02:12:08 -0400","by mail-pf0-f170.google.com with SMTP id e199so12617359pfh.3\n\tfor ;\n\tSun, 10 Sep 2017 23:12:08 -0700 (PDT)","from localhost.localdomain (125-227-158-176.HINET-IP.hinet.net.\n\t[125.227.158.176]) by smtp.gmail.com with ESMTPSA id\n\tp5sm12919837pgc.94.2017.09.10.23.12.04\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 10 Sep 2017 23:12:07 -0700 (PDT)"],"DKIM-Signature":"v=1; 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\n\tSun, 10 Sep 2017 23:12:08 -0700 (PDT)","From":"Daniel Drake ","To":"linus.walleij@linaro.org","Cc":"linux-gpio@vger.kernel.org, Nehal-bakulchandra.Shah@amd.com,\n\tShyam-sundar.S-k@amd.com, linux@endlessm.com","Subject":"[PATCH] pinctrl/amd: save pin registers over suspend/resume","Date":"Mon, 11 Sep 2017 14:11:56 +0800","Message-Id":"<20170911061156.31872-1-drake@endlessm.com>","X-Mailer":"git-send-email 2.11.0","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"The touchpad in the Asus laptop models X505BA/BP and X542BA/BP is\nunresponsive after suspend/resume. The following error appears during\nresume:\n\n i2c_hid i2c-ELAN1300:00: failed to reset device.\n\nThe problem here is that i2c_hid does not notice the interrupt being\ngenerated at this point, because the GPIO is no longer configured\nfor interrupts.\n\nFix this by saving pinctrl-amd pin registers during suspend and\nrestoring them at resume time.\n\nBased on code from pinctrl-intel.\n\nSigned-off-by: Daniel Drake \n---\n drivers/pinctrl/pinctrl-amd.c | 75 +++++++++++++++++++++++++++++++++++++++++++\n drivers/pinctrl/pinctrl-amd.h | 1 +\n 2 files changed, 76 insertions(+)","diff":"diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c\nindex 38af1ec2df0c..3f6b34febbf1 100644\n--- a/drivers/pinctrl/pinctrl-amd.c\n+++ b/drivers/pinctrl/pinctrl-amd.c\n@@ -36,6 +36,7 @@\n #include \n #include \n \n+#include \"core.h\"\n #include \"pinctrl-utils.h\"\n #include \"pinctrl-amd.h\"\n \n@@ -725,6 +726,69 @@ static const struct pinconf_ops amd_pinconf_ops = {\n \t.pin_config_group_set = amd_pinconf_group_set,\n };\n \n+#ifdef CONFIG_PM_SLEEP\n+static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)\n+{\n+\tconst struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);\n+\n+\tif (!pd)\n+\t\treturn false;\n+\n+\t/*\n+\t * Only restore the pin if it is actually in use by the kernel (or\n+\t * by userspace).\n+\t */\n+\tif (pd->mux_owner || pd->gpio_owner ||\n+\t gpiochip_line_is_irq(&gpio_dev->gc, pin))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+int amd_gpio_suspend(struct device *dev)\n+{\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct amd_gpio *gpio_dev = platform_get_drvdata(pdev);\n+\tstruct pinctrl_desc *desc = gpio_dev->pctrl->desc;\n+\tint i;\n+\n+\tfor (i = 0; i < desc->npins; i++) {\n+\t\tint pin = desc->pins[i].number;\n+\n+\t\tif (!amd_gpio_should_save(gpio_dev, pin))\n+\t\t\tcontinue;\n+\n+\t\tgpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int amd_gpio_resume(struct device *dev)\n+{\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct amd_gpio *gpio_dev = platform_get_drvdata(pdev);\n+\tstruct pinctrl_desc *desc = gpio_dev->pctrl->desc;\n+\tint i;\n+\n+\tfor (i = 0; i < desc->npins; i++) {\n+\t\tint pin = desc->pins[i].number;\n+\n+\t\tif (!amd_gpio_should_save(gpio_dev, pin))\n+\t\t\tcontinue;\n+\n+\t\twritel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct dev_pm_ops amd_gpio_pm_ops = {\n+\tSET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,\n+\t\t\t\t amd_gpio_resume)\n+};\n+#endif\n+\n static struct pinctrl_desc amd_pinctrl_desc = {\n \t.pins\t= kerncz_pins,\n \t.npins = ARRAY_SIZE(kerncz_pins),\n@@ -764,6 +828,14 @@ static int amd_gpio_probe(struct platform_device *pdev)\n \t\treturn irq_base;\n \t}\n \n+#ifdef CONFIG_PM_SLEEP\n+\tgpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,\n+\t\t\t\t\t sizeof(*gpio_dev->saved_regs),\n+\t\t\t\t\t GFP_KERNEL);\n+\tif (!gpio_dev->saved_regs)\n+\t\treturn -ENOMEM;\n+#endif\n+\n \tgpio_dev->pdev = pdev;\n \tgpio_dev->gc.direction_input\t= amd_gpio_direction_input;\n \tgpio_dev->gc.direction_output\t= amd_gpio_direction_output;\n@@ -853,6 +925,9 @@ static struct platform_driver amd_gpio_driver = {\n \t.driver\t\t= {\n \t\t.name\t= \"amd_gpio\",\n \t\t.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),\n+#ifdef CONFIG_PM_SLEEP\n+\t\t.pm\t= &amd_gpio_pm_ops,\n+#endif\n \t},\n \t.probe\t\t= amd_gpio_probe,\n \t.remove\t\t= amd_gpio_remove,\ndiff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h\nindex 5b1cb965c767..8fa453a59da5 100644\n--- a/drivers/pinctrl/pinctrl-amd.h\n+++ b/drivers/pinctrl/pinctrl-amd.h\n@@ -97,6 +97,7 @@ struct amd_gpio {\n \tunsigned int hwbank_num;\n \tstruct resource *res;\n \tstruct platform_device *pdev;\n+\tu32\t\t\t*saved_regs;\n };\n \n /* KERNCZ configuration*/\n","prefixes":[]}