{"id":811809,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811809/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170908190825.21515-2-s-anna@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170908190825.21515-2-s-anna@ti.com>","list_archive_url":null,"date":"2017-09-08T19:08:24","name":"[U-Boot,1/2] arm: am57xx: cl-som-am57x: Use new pinctrl macros","commit_ref":"101d2171e10951d115fd9229c5edc883f1833e96","pull_url":null,"state":"accepted","archived":false,"hash":"6548ae11f720d9057048828e363fe945c2685cdc","submitter":{"id":24498,"url":"http://patchwork.ozlabs.org/api/1.2/people/24498/?format=json","name":"Suman Anna","email":"s-anna@ti.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170908190825.21515-2-s-anna@ti.com/mbox/","series":[{"id":2278,"url":"http://patchwork.ozlabs.org/api/1.2/series/2278/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=2278","date":"2017-09-08T19:08:23","name":"Cleanup old DRA7 pinctrl macros","version":1,"mbox":"http://patchwork.ozlabs.org/series/2278/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811809/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811809/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1504897716;\n\tbh=XJZzJXEA/umRuhp/elhW0ZXFmlQGsL4PgVJFdqu0+Ec=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=lR1MZf5ODIAm5VTBkdPF9VMQG9sxBjrOnaHMBR6VI9PvYJkd5xOzQaWLdrw+KJUpq\n\t0zdVtzF2T2VTF8n8QsmGBehXVHzcVyS/lcMDretre5455Mqztl0ddKjToIe366NtgN\n\t1M/TYPfFv0uf51vGQeRNz3Fj6UiLeJBO7XcfvGi4=","From":"Suman Anna ","To":"Uri Mashiach ","Date":"Fri, 8 Sep 2017 14:08:24 -0500","Message-ID":"<20170908190825.21515-2-s-anna@ti.com>","X-Mailer":"git-send-email 2.13.1","In-Reply-To":"<20170908190825.21515-1-s-anna@ti.com>","References":"<20170908190825.21515-1-s-anna@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"Tom Rini , u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH 1/2] arm: am57xx: cl-som-am57x: Use new pinctrl\n\tmacros","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Commit 6ae4c3efbd62 (\"ARM: DRA7: Add pinctrl register definitions\")\nhas added new macros for pinmux configuration in line with the\nkernel definitions. Fixup the current pinctrl data for the CompuLab\nCL-SOM-AM57x board to use these new macros to facilitate the removal\nof the old macros.\n\nNOTE:\nThe PEN and PDIS macro values used previously were actually defined\ninversely, a value of 1 in bit position 16 actually means that the\ninternal pullup/pulldown is disabled and not enabled as inferred by\nPEN. So, previous pinmux config data such as (PDIS | PTU) is confusing\nas it actually was meant for enabling internal pullup. The data is\nfixed up only to be equivalent to the previous data.\n\nSigned-off-by: Suman Anna \n---\n board/compulab/cl-som-am57x/mux.c | 105 +++++++++++++++++++-------------------\n 1 file changed, 53 insertions(+), 52 deletions(-)","diff":"diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c\nindex 0db0609727f7..21449ca029b0 100644\n--- a/board/compulab/cl-som-am57x/mux.c\n+++ b/board/compulab/cl-som-am57x/mux.c\n@@ -12,97 +12,98 @@\n \n /* Serial console */\n static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {\n-\t{UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */\n-\t{UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */\n+\t{UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */\n+\t{UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */\n };\n \n /* PMIC I2C */\n static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {\n-\t{MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */\n-\t{MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */\n+\t{MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */\n+\t{MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */\n };\n \n /* Green GPIO led */\n static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {\n-\t{GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */\n+\t{GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */\n };\n \n /* MMC/SD Card */\n static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {\n-\t{MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */\n-\t{MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */\n-\t{MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */\n-\t{MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */\n-\t{MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */\n-\t{MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */\n-\t{MMC1_SDCD, (IEN | PEN |\tM14)}, /* MMC1_SDCD */\n-\t{MMC1_SDWP, (IEN | PEN |\tM14)}, /* MMC1_SDWP */\n+\t{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */\n+\t{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */\n+\t{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */\n+\t{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */\n+\t{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */\n+\t{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */\n+\t{MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */\n+\t{MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */\n };\n \n /* WiFi - must be in the safe mode on boot */\n static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {\n-\t{UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */\n-\t{UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */\n-\t{UART2_RXD, (IEN | M15)}, /* UART2_RXD */\n-\t{UART2_TXD, (IEN | M15)}, /* UART2_TXD */\n-\t{UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */\n-\t{UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */\n+\t{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */\n+\t{UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */\n+\t{UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */\n+\t{UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */\n+\t{UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */\n+\t{UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */\n };\n \n /* QSPI */\n static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {\n-\t{GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */\n-\t{GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */\n-\t{GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */\n-\t{GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */\n-\t{GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */\n+\t{GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */\n+\t{GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */\n+\t{GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */\n+\t{GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */\n+\t{GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */\n };\n \n /* GPIO Expander I2C */\n static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {\n-\t{MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */\n-\t{MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */\n+\t{MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */\n+\t{MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */\n };\n \n /* eMMC internal storage */\n static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {\n-\t{GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */\n-\t{GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */\n-\t{GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */\n-\t{GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */\n-\t{GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */\n-\t{GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */\n-\t{GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */\n-\t{GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */\n-\t{GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */\n-\t{GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */\n+\t{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */\n+\t{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */\n+\t{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */\n+\t{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */\n+\t{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */\n+\t{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */\n+\t{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */\n+\t{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */\n+\t{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */\n+\t{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */\n };\n \n /* usb1_drvvbus */\n static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {\n-\t{USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */\n+\t/* USB1_DRVVBUS.USB1_DRVVBUS */\n+\t{USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) },\n };\n \n /* Ethernet */\n static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {\n \t/* MDIO bus */\n-\t{VIN2A_D10, (PDIS | PTU |\t M3) }, /* VIN2A_D10.MDIO_MCLK */\n-\t{VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */\n+\t{VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */\n+\t{VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */\n \t/* EMAC Slave 1 at addr 0x1 - Default interface */\n-\t{VIN2A_D12, (IDIS | PEN |\t M3) }, /* VIN2A_D12.RGMII1_TXC */\n-\t{VIN2A_D13, (IDIS | PEN |\t M3) }, /* VIN2A_D13.RGMII1_TXCTL */\n-\t{VIN2A_D14, (IDIS | PEN |\t M3) }, /* VIN2A_D14.RGMII1_TXD3 */\n-\t{VIN2A_D15, (IDIS | PEN |\t M3) }, /* VIN2A_D15.RGMII1_TXD2 */\n-\t{VIN2A_D16, (IDIS | PEN |\t M3) }, /* VIN2A_D16.RGMII1_TXD1 */\n-\t{VIN2A_D17, (IDIS | PEN |\t M3) }, /* VIN2A_D17.RGMII1_TXD0 */\n-\t{VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */\n-\t{VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */\n-\t{VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */\n-\t{VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */\n-\t{VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */\n-\t{VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */\n+\t{VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */\n+\t{VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */\n+\t{VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */\n+\t{VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */\n+\t{VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */\n+\t{VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */\n+\t{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */\n+\t{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */\n+\t{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */\n+\t{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */\n+\t{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */\n+\t{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */\n \t/* Eth PHY1 reset GPIOs*/\n-\t{VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */\n+\t{VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */\n };\n \n #define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \\\n","prefixes":["U-Boot","1/2"]}