{"id":811802,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811802/?format=json","web_url":"http://patchwork.ozlabs.org/project/lede/patch/1504897019-9633-1-git-send-email-tharvey@gateworks.com/","project":{"id":54,"url":"http://patchwork.ozlabs.org/api/1.2/projects/54/?format=json","name":"LEDE development","link_name":"lede","list_id":"lede-dev.lists.infradead.org","list_email":"lede-dev@lists.infradead.org","web_url":"http://lede-project.org/","scm_url":"","webscm_url":"http://git.lede-project.org/","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504897019-9633-1-git-send-email-tharvey@gateworks.com>","list_archive_url":null,"date":"2017-09-08T18:56:59","name":"[LEDE-DEV] cns3xxx: fix GPIO controller interrupt enable","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"a4d06d208b9efb4f52189100bccc5a6843e39a31","submitter":{"id":41730,"url":"http://patchwork.ozlabs.org/api/1.2/people/41730/?format=json","name":"Tim Harvey","email":"tharvey@gateworks.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/lede/patch/1504897019-9633-1-git-send-email-tharvey@gateworks.com/mbox/","series":[{"id":2276,"url":"http://patchwork.ozlabs.org/api/1.2/series/2276/?format=json","web_url":"http://patchwork.ozlabs.org/project/lede/list/?series=2276","date":"2017-09-08T18:56:59","name":"[LEDE-DEV] cns3xxx: fix GPIO controller interrupt enable","version":1,"mbox":"http://patchwork.ozlabs.org/series/2276/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811802/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811802/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=lede-dev-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"ltypUIjc\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gateworks-com.20150623.gappssmtp.com\n\theader.i=@gateworks-com.20150623.gappssmtp.com\n\theader.b=\"GBimBA50\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpmhT68CFz9sRV\n\tfor ;\n\tSat, 9 Sep 2017 04:54:33 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dqOPx-0000hZ-Gh; Fri, 08 Sep 2017 18:54:17 +0000","from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dqOPt-0000dd-P7\n\tfor lede-dev@lists.infradead.org; Fri, 08 Sep 2017 18:54:15 +0000","by mail-pf0-x22a.google.com with SMTP id e1so5821432pfk.1\n\tfor ;\n\tFri, 08 Sep 2017 11:53:52 -0700 (PDT)","from tharvey.pdc.gateworks.com\n\t(68-189-91-139.static.snlo.ca.charter.com. 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When one\nwould get enabled all others would be disabled prior to this patch.\n\nSigned-off-by: Tim Harvey \n---\n target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)","diff":"diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c\nindex 19de24c..bdf930a 100644\n--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c\n+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c\n@@ -273,10 +273,10 @@ void __init cns3xxx_gpio_init(int gpio_base, int ngpio,\n \tct = gc->chip_types;\n \tct->type = IRQ_TYPE_EDGE_FALLING;\n \tct->regs.ack = GPIO_INTERRUPT_CLEAR;\n-\tct->regs.enable = GPIO_INTERRUPT_ENABLE;\n \tct->chip.irq_ack = irq_gc_ack_set_bit;\n-\tct->chip.irq_enable = irq_gc_unmask_enable_reg;\n-\tct->chip.irq_disable = irq_gc_mask_disable_reg;\n+\tct->regs.mask = GPIO_INTERRUPT_ENABLE;\n+\tct->chip.irq_enable = irq_gc_mask_set_bit;\n+\tct->chip.irq_disable = irq_gc_mask_clr_bit;\n \tct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;\n \tct->handler = handle_edge_irq;\n \n","prefixes":["LEDE-DEV"]}