{"id":811621,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811621/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504880304-12069-7-git-send-email-mst@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504880304-12069-7-git-send-email-mst@redhat.com>","list_archive_url":null,"date":"2017-09-08T14:19:12","name":"[PULL,06/17] hw/pci: introduce pcie-pci-bridge device","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"79da4df7afe1b1a17111111fbe022066b8c75f53","submitter":{"id":2235,"url":"http://patchwork.ozlabs.org/api/1.2/people/2235/?format=json","name":"Michael S. Tsirkin","email":"mst@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504880304-12069-7-git-send-email-mst@redhat.com/mbox/","series":[{"id":2227,"url":"http://patchwork.ozlabs.org/api/1.2/series/2227/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2227","date":"2017-09-08T14:18:52","name":"[PULL,01/17] vhost: Release memory references on cleanup","version":1,"mbox":"http://patchwork.ozlabs.org/series/2227/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811621/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811621/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx09.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx09.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=mst@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpfbk30l6z9s71\n\tfor ;\n\tSat, 9 Sep 2017 00:20:02 +1000 (AEST)","from localhost ([::1]:45669 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dqK8W-0006c3-CQ\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 10:20:00 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:49023)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dqK7o-0006Zr-0F\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 10:19:17 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dqK7m-0004un-Mv\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 10:19:15 -0400","from mx1.redhat.com ([209.132.183.28]:41478)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dqK7m-0004td-Dv\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 10:19:14 -0400","from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 84B234A703;\n\tFri, 8 Sep 2017 14:19:13 +0000 (UTC)","from redhat.com (ovpn-120-144.rdu2.redhat.com [10.10.120.144])\n\tby smtp.corp.redhat.com (Postfix) with SMTP id E41B560605;\n\tFri, 8 Sep 2017 14:19:12 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 84B234A703","Date":"Fri, 8 Sep 2017 17:19:12 +0300","From":"\"Michael S. Tsirkin\" ","To":"qemu-devel@nongnu.org","Message-ID":"<1504880304-12069-7-git-send-email-mst@redhat.com>","References":"<1504880304-12069-1-git-send-email-mst@redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504880304-12069-1-git-send-email-mst@redhat.com>","X-Mutt-Fcc":"=sent","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.13","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.38]);\n\tFri, 08 Sep 2017 14:19:13 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PULL 06/17] hw/pci: introduce pcie-pci-bridge device","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Marcel Apfelbaum ,\n\tPeter Maydell ,\n\tAleksandr Bezzubikov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Aleksandr Bezzubikov \n\nIntroduce a new PCIExpress-to-PCI Bridge device,\nwhich is a hot-pluggable PCI Express device and\nsupports devices hot-plug with SHPC.\n\nThis device is intended to replace the DMI-to-PCI Bridge.\n\nSigned-off-by: Aleksandr Bezzubikov \nReviewed-by: Marcel Apfelbaum \nTested-by: Marcel Apfelbaum \nReviewed-by: Michael S. Tsirkin \nSigned-off-by: Michael S. Tsirkin \n---\n include/hw/pci/pci.h | 1 +\n hw/pci-bridge/pcie_pci_bridge.c | 192 ++++++++++++++++++++++++++++++++++++++++\n hw/pci-bridge/Makefile.objs | 2 +-\n 3 files changed, 194 insertions(+), 1 deletion(-)\n create mode 100644 hw/pci-bridge/pcie_pci_bridge.c","diff":"diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h\nindex 8bb6449..aa7ef9c 100644\n--- a/include/hw/pci/pci.h\n+++ b/include/hw/pci/pci.h\n@@ -100,6 +100,7 @@ extern bool pci_available;\n #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b\n #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c\n #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d\n+#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e\n #define PCI_DEVICE_ID_REDHAT_QXL 0x0100\n \n #define FMT_PCIBUS PRIx64\ndiff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c\nnew file mode 100644\nindex 0000000..9aa5cc3\n--- /dev/null\n+++ b/hw/pci-bridge/pcie_pci_bridge.c\n@@ -0,0 +1,192 @@\n+/*\n+ * QEMU Generic PCIE-PCI Bridge\n+ *\n+ * Copyright (c) 2017 Aleksandr Bezzubikov\n+ *\n+ * This work is licensed under the terms of the GNU GPL, version 2 or later.\n+ * See the COPYING file in the top-level directory.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qapi/error.h\"\n+#include \"hw/pci/pci.h\"\n+#include \"hw/pci/pci_bus.h\"\n+#include \"hw/pci/pci_bridge.h\"\n+#include \"hw/pci/msi.h\"\n+#include \"hw/pci/shpc.h\"\n+#include \"hw/pci/slotid_cap.h\"\n+\n+typedef struct PCIEPCIBridge {\n+ /*< private >*/\n+ PCIBridge parent_obj;\n+\n+ OnOffAuto msi;\n+ MemoryRegion shpc_bar;\n+ /*< public >*/\n+} PCIEPCIBridge;\n+\n+#define TYPE_PCIE_PCI_BRIDGE_DEV \"pcie-pci-bridge\"\n+#define PCIE_PCI_BRIDGE_DEV(obj) \\\n+ OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV)\n+\n+static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)\n+{\n+ PCIBridge *br = PCI_BRIDGE(d);\n+ PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d);\n+ int rc, pos;\n+\n+ pci_bridge_initfn(d, TYPE_PCI_BUS);\n+\n+ d->config[PCI_INTERRUPT_PIN] = 0x1;\n+ memory_region_init(&pcie_br->shpc_bar, OBJECT(d), \"shpc-bar\",\n+ shpc_bar_size(d));\n+ rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp);\n+ if (rc) {\n+ goto error;\n+ }\n+\n+ rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp);\n+ if (rc < 0) {\n+ goto cap_error;\n+ }\n+\n+ pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp);\n+ if (pos < 0) {\n+ goto pm_error;\n+ }\n+ d->exp.pm_cap = pos;\n+ pci_set_word(d->config + pos + PCI_PM_PMC, 0x3);\n+\n+ pcie_cap_arifwd_init(d);\n+ pcie_cap_deverr_init(d);\n+\n+ rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp);\n+ if (rc < 0) {\n+ goto aer_error;\n+ }\n+\n+ if (pcie_br->msi != ON_OFF_AUTO_OFF) {\n+ rc = msi_init(d, 0, 1, true, true, errp);\n+ if (rc < 0) {\n+ goto msi_error;\n+ }\n+ }\n+ pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |\n+ PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar);\n+ return;\n+\n+msi_error:\n+ pcie_aer_exit(d);\n+aer_error:\n+pm_error:\n+ pcie_cap_exit(d);\n+cap_error:\n+ shpc_free(d);\n+error:\n+ pci_bridge_exitfn(d);\n+}\n+\n+static void pcie_pci_bridge_exit(PCIDevice *d)\n+{\n+ PCIEPCIBridge *bridge_dev = PCIE_PCI_BRIDGE_DEV(d);\n+ pcie_cap_exit(d);\n+ shpc_cleanup(d, &bridge_dev->shpc_bar);\n+ pci_bridge_exitfn(d);\n+}\n+\n+static void pcie_pci_bridge_reset(DeviceState *qdev)\n+{\n+ PCIDevice *d = PCI_DEVICE(qdev);\n+ pci_bridge_reset(qdev);\n+ msi_reset(d);\n+ shpc_reset(d);\n+}\n+\n+static void pcie_pci_bridge_write_config(PCIDevice *d,\n+ uint32_t address, uint32_t val, int len)\n+{\n+ pci_bridge_write_config(d, address, val, len);\n+ msi_write_config(d, address, val, len);\n+ shpc_cap_write_config(d, address, val, len);\n+}\n+\n+static Property pcie_pci_bridge_dev_properties[] = {\n+ DEFINE_PROP_ON_OFF_AUTO(\"msi\", PCIEPCIBridge, msi, ON_OFF_AUTO_ON),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static const VMStateDescription pcie_pci_bridge_dev_vmstate = {\n+ .name = TYPE_PCIE_PCI_BRIDGE_DEV,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),\n+ SHPC_VMSTATE(shpc, PCIDevice, NULL),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev,\n+ DeviceState *dev, Error **errp)\n+{\n+ PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);\n+\n+ if (!shpc_present(pci_hotplug_dev)) {\n+ error_setg(errp, \"standard hotplug controller has been disabled for \"\n+ \"this %s\", TYPE_PCIE_PCI_BRIDGE_DEV);\n+ return;\n+ }\n+ shpc_device_hotplug_cb(hotplug_dev, dev, errp);\n+}\n+\n+static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_dev,\n+ DeviceState *dev,\n+ Error **errp)\n+{\n+ PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);\n+\n+ if (!shpc_present(pci_hotplug_dev)) {\n+ error_setg(errp, \"standard hotplug controller has been disabled for \"\n+ \"this %s\", TYPE_PCIE_PCI_BRIDGE_DEV);\n+ return;\n+ }\n+ shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp);\n+}\n+\n+static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)\n+{\n+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);\n+\n+ k->is_express = 1;\n+ k->is_bridge = 1;\n+ k->vendor_id = PCI_VENDOR_ID_REDHAT;\n+ k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;\n+ k->realize = pcie_pci_bridge_realize;\n+ k->exit = pcie_pci_bridge_exit;\n+ k->config_write = pcie_pci_bridge_write_config;\n+ dc->vmsd = &pcie_pci_bridge_dev_vmstate;\n+ dc->props = pcie_pci_bridge_dev_properties;\n+ dc->vmsd = &pcie_pci_bridge_dev_vmstate;\n+ dc->reset = &pcie_pci_bridge_reset;\n+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);\n+ hc->plug = pcie_pci_bridge_hotplug_cb;\n+ hc->unplug_request = pcie_pci_bridge_hot_unplug_request_cb;\n+}\n+\n+static const TypeInfo pcie_pci_bridge_info = {\n+ .name = TYPE_PCIE_PCI_BRIDGE_DEV,\n+ .parent = TYPE_PCI_BRIDGE,\n+ .instance_size = sizeof(PCIEPCIBridge),\n+ .class_init = pcie_pci_bridge_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { TYPE_HOTPLUG_HANDLER },\n+ { },\n+ }\n+};\n+\n+static void pciepci_register(void)\n+{\n+ type_register_static(&pcie_pci_bridge_info);\n+}\n+\n+type_init(pciepci_register);\ndiff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs\nindex c4683cf..666db37 100644\n--- a/hw/pci-bridge/Makefile.objs\n+++ b/hw/pci-bridge/Makefile.objs\n@@ -1,4 +1,4 @@\n-common-obj-y += pci_bridge_dev.o\n+common-obj-y += pci_bridge_dev.o pcie_pci_bridge.o\n common-obj-$(CONFIG_PCIE_PORT) += pcie_root_port.o gen_pcie_root_port.o\n common-obj-$(CONFIG_PXB) += pci_expander_bridge.o\n common-obj-$(CONFIG_XIO3130) += xio3130_upstream.o xio3130_downstream.o\n","prefixes":["PULL","06/17"]}