{"id":811262,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811262/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-23-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-23-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:50","name":"[PULL,22/23] tcg/ppc: Look for shifted constants","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"825c138154249f599aeb84281636ad3c8924bcfc","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-23-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811262/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811262/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Note that we've already\n+ eliminated bare ADDIS, so we know both insns are required. */\n if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {\n tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));\n- if (arg & 0xffff) {\n- tcg_out32(s, ORI | SAI(ret, ret, arg));\n- }\n+ tcg_out32(s, ORI | SAI(ret, ret, arg));\n return;\n }\n if (arg == (uint32_t)arg && !(arg & 0x8000)) {\n@@ -632,15 +645,40 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n return;\n }\n \n+ /* Load masked 16-bit value. */\n+ if (arg > 0 && (arg & 0x8000)) {\n+ tmp = arg | 0x7fff;\n+ if ((tmp & (tmp + 1)) == 0) {\n+ int mb = clz64(tmp + 1) + 1;\n+ tcg_out32(s, ADDI | TAI(ret, 0, arg));\n+ tcg_out_rld(s, RLDICL, ret, ret, 0, mb);\n+ return;\n+ }\n+ }\n+\n+ /* Load common masks with 2 insns. */\n+ shift = ctz64(arg);\n+ tmp = arg >> shift;\n+ if (tmp == (int16_t)tmp) {\n+ tcg_out32(s, ADDI | TAI(ret, 0, tmp));\n+ tcg_out_shli64(s, ret, ret, shift);\n+ return;\n+ }\n+ shift = clz64(arg);\n+ if (tcg_out_movi_one(s, ret, arg << shift)) {\n+ tcg_out_shri64(s, ret, ret, shift);\n+ return;\n+ }\n+\n /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */\n if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {\n tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);\n return;\n }\n \n- high = arg >> 31 >> 1;\n- tcg_out_movi(s, TCG_TYPE_I32, ret, high);\n- if (high) {\n+ tmp = arg >> 31 >> 1;\n+ tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);\n+ if (tmp) {\n tcg_out_shli64(s, ret, ret, 32);\n }\n if (arg & 0xffff0000) {\n","prefixes":["PULL","22/23"]}